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Articles 421 - 450 of 488

Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems

Hand-Held Flyback Driven Coaxial Dielectric Barrier Discharge: Development And Characterization, Victor J. Law, Vladimir Milosavljevic, Neil O’Connor, James F. Lalor, Steven Daniels Sep 2008

Hand-Held Flyback Driven Coaxial Dielectric Barrier Discharge: Development And Characterization, Victor J. Law, Vladimir Milosavljevic, Neil O’Connor, James F. Lalor, Steven Daniels

Articles

The development of a handheld single and triple chamber atmospheric pressure coaxial dielectric barrier discharge driven by Flyback circuitry for helium and argon discharges is described. The Flyback uses external metal-oxide-semiconductor field-effect transistor power switching technology and the transformer operates in the continuous current mode to convert a continuous dc power of 10–33 W to generate a 1.2–1.6 kV 3.5 μs pulse. An argon discharge breakdown voltage of ∼768 V is measured. With a 50 kHz, pulse repetition rate and an argon flow rate of 0.5–10 argon slm (slm denotes standard liters per minute), the electrical power density deposited in …


A Modular Mixed Signal Vlsi Design Approach For Digital Radar Applications, Brian M. Brakus Mar 2007

A Modular Mixed Signal Vlsi Design Approach For Digital Radar Applications, Brian M. Brakus

Theses and Dissertations

This study explores the idea of building a library of VHDL configurable components for use in digital radar applications. Configurable components allows a designer to choose which components he or she needs and configures those components for a specific application. By doing this, design time for ASICs and FPGAs is shortened because the components are already designed and tested. This idea is demonstrated with a configurable dynamic pipelinable fast fourier transform. Many FFT implementations exist, but this implementation is both configurable and dynamic. Pre-synthesis customization allows the FFT to be tailored to almost any DSP application, and the dynamic property …


Asynchronous Ds-Ss Cdma Random Spreading Code Correlation Statistics In The Presence Of Timing Error, David W. Matolak Nov 2005

Asynchronous Ds-Ss Cdma Random Spreading Code Correlation Statistics In The Presence Of Timing Error, David W. Matolak

Faculty Publications

We quantify the effect of timing tracking errors upon 2nd order correlation statistics of random binary spreading codes and, in so doing, fill a gap in the literature. Using a Gaussian model for timing tracking error, new expressions for autocorrelation statistics are derived. For crosscorrelations, we show that a zero mean Gaussian timing error has no effect upon 2nd order crosscorrelation statistics.


A Dsp-Based Active Disturbance Rejection Control Design For A 1-Kw H-Bridge Dc-Dc Power Converter, Bosheng Sun, Zhiqiang Gao Oct 2005

A Dsp-Based Active Disturbance Rejection Control Design For A 1-Kw H-Bridge Dc-Dc Power Converter, Bosheng Sun, Zhiqiang Gao

Electrical and Computer Engineering Faculty Publications

This paper presents the design and implementation of an advanced digital controller for a 1-kW H-bridge dc-dc power converter. A new control algorithm based on the active disturbance rejection concept is developed to cope with the highly nonlinear dynamics of the converter and the disturbances. An experimental digital control system is used to implement the new control strategy. It consists of a digital control board based on the TMS320C6711 digital signal processor chip, an analogy I/O board, and a complex programmable logic device pulsewidth-modulation generation board. Using a newly developed bandwidth-parametrization technique, an autotuning method based on noise quantification is …


A Multiplier-Less Architecture For High Speed Computation Of Multi-Dimensional Convolution, Ming Zhu Zhang Jul 2005

A Multiplier-Less Architecture For High Speed Computation Of Multi-Dimensional Convolution, Ming Zhu Zhang

Electrical & Computer Engineering Theses & Dissertations

One of the most computationally intensive operations in digital image/video processing systems is multi-dimensional convolution. Every image/video processor needs the convolution module in its pre-processing stage. Fast and efficient design of the convolution module in an application specific system is a great challenge in VLSI (Very Large Scale Integration) design. Convolution operator requires a large set of multipliers and accumulators. A high precision multiplier takes enormous amount of VLSI area and it consumes more power. Hence reduction of the number of multipliers is another important challenge in VLSI design. A multiplier-less architecture for the design of a multi-dimensional convolution module …


Opto-Vlsi Based Wdm Multifunction Device, Selam T. Ahderom Jan 2004

Opto-Vlsi Based Wdm Multifunction Device, Selam T. Ahderom

Theses: Doctorates and Masters

The tremendous expansion of telecommunication services in the past decade, in part due to the growth of the Internet, has made the development of high-bandwidth optical net-works a focus of research interest. The implementation of Dense-Wavelength Division Multiplexing (DWDM) optical fiber transmission systems has the potential to meet this demand. However, crucial components of DWDM networks – add/drop multiplexers, filters, gain equalizers as well as interconnects between optical channels – are currently not implemented as dynamically reconfigurable devices. Electronic cross-connects, the traditional solution to the reconfigurable optical networks, are increasingly not feasible due to the rapidly increasing bandwidth of the …


Adaptive Applications Of Opto-Vlsi Processors In Wdm Networks, Mehrdad Raisi Jan 2004

Adaptive Applications Of Opto-Vlsi Processors In Wdm Networks, Mehrdad Raisi

Theses: Doctorates and Masters

Communication is an inseparable part of human life and its nature continues to evolve and improve. The advent of laser was a herald to the new possibilities in the communication world. In recent years technologies such as Wavelength Division Multiplexing (WDM) and Erbium Doped Fiber Amplifiers (EDFA) have afforded significant boost to the practice of optical communication. At the heart of this brave new world is the need to dynamically/ adaptively steer/route beams of light carrying very large amounts of data. In recent years many techniques have been proposed for this purpose by various researchers. In this study we have …


Unidirectional Cordic For Efficient Computation Of Trigonometric And Hyperbolic Functions, Satish Ravichandran Oct 2003

Unidirectional Cordic For Efficient Computation Of Trigonometric And Hyperbolic Functions, Satish Ravichandran

Electrical & Computer Engineering Theses & Dissertations

CORDIC (Coordinate Rotation Digital Computer) is an iterative algorithm to compute values of trigonometric, logarithmic and transcendental functions by performing vector rotations, which can be implemented with only shift and add operations in a digital system. CORDIC algorithms are extensively used in the areas of digital signal processing, digital image processing and artificial neural networks. A new technique, named unidirectional CORDIC, for efficient computation of trigonometric and hyperbolic functions is presented in this thesis. In the conventional CORDIC algorithm, the vector rotations are performed in both clockwise and counterclockwise directions, but in the unidirectional CORDIC the vectors are rotated only …


Monte Carlo Analysis Of Millimeter-Wave Gan Based Gunn Effect Oscillators, Sridhara Viswanadham Jul 2003

Monte Carlo Analysis Of Millimeter-Wave Gan Based Gunn Effect Oscillators, Sridhara Viswanadham

Electrical & Computer Engineering Theses & Dissertations

Gunn diodes are one of the most common high frequency solid-state oscillators at the present time, and are considered as promising devices for millimeter and submillimeter wave applications. Monte Carlo studies of Gunn diodes based on bulk wurtzite GaN have been carried out in this thesis research. Two structures have been examined: (i) devices with conventional single notch structure and (ii) repetitive structures with serial segments to fashion a "multiple domain" device. Wurtzite GaN has been chosen because of the high drift velocity and because analytical expressions for the band structure have recently become available. Performance parameters of interest such …


Parallel Implementation Of A Face Recognition [Sic] System Based On Modular Pca Approach, Rajkiran Gottumukkal Apr 2003

Parallel Implementation Of A Face Recognition [Sic] System Based On Modular Pca Approach, Rajkiran Gottumukkal

Electrical & Computer Engineering Theses & Dissertations

This thesis describes research in automated methods for the recognition of human faces. The research is driven by the need to design a method, which would ensure high accuracy under the conditions of facial expression, illumination and pose variations. The resulting method is able to cope with uncontrolled nature of facial expression, illumination and head rotations. The main novelty of this work is the idea that some of the local facial features do not vary even when the facial expression, illumination and pose vary. This idea is applied to the existing principle component analysis lPCA) method to arrive at a …


Design For Signal Integrity In High Frequency, High Density Circuit Boards, Juan Manuel Talavera Martinez Jan 2003

Design For Signal Integrity In High Frequency, High Density Circuit Boards, Juan Manuel Talavera Martinez

Theses

The electronics market is continually seeking fast and small high performance products. The clock frequency in computer systems is often above 2GHz and new generations of laptops have considerably reduced in size. These features make printed circuit board (PCB) design more difficult than in the past.

This thesis is an investigation of the current design of high speed PCB. The complexity of this type of circuit makes the designer needs an extensive knowledge of the techniques used to generate a reliable signalling, in other words, signal integrity. To achieve this objective, the design community has to overcome several problem related …


Novel High Frequency Silicon Carbide Static Induction Transistor-Based Test-Bed For The Acquisition Of Sic Power Device Reverse Recovery Characteristics, Kevin M. Speer, Ty R. Mcnutt, Alexander B. Lostetter, H. Alan Mantooth, Kraig J. Olejniczak Jan 2003

Novel High Frequency Silicon Carbide Static Induction Transistor-Based Test-Bed For The Acquisition Of Sic Power Device Reverse Recovery Characteristics, Kevin M. Speer, Ty R. Mcnutt, Alexander B. Lostetter, H. Alan Mantooth, Kraig J. Olejniczak

Journal of the Arkansas Academy of Science

A test system is presented that utilizes a high-frequency Silicon Carbide (SiC) Static Induction Transistor (SIT) in place of the traditional MOSFET to test reverse recovery characteristics for the new class of SiC power diodes. An easily implementable drive circuit is presented that can drive the high-frequency SIT. The SiC SIT is also compared to a commonly used Si MOSFET in the test circuit application.


Parameter Extraction Software For Compact Diode Model, Maruf Hossain, Edgar Cilio, Ty R. Mcnutt, Alexander B. Lostetter, H. Alan Mantooth Jan 2003

Parameter Extraction Software For Compact Diode Model, Maruf Hossain, Edgar Cilio, Ty R. Mcnutt, Alexander B. Lostetter, H. Alan Mantooth

Journal of the Arkansas Academy of Science

No abstract provided.


Testing And Modeling Electrical Characteristics Of Novel Silicon Carbide (Sic) Static Induction Transistors (Sits), Avinash S. Kashyap, Sharmila D. Mangan Lal, Ty R. Mcnutt, Alexander B. Lostetter, H. Alan Mantooth Jan 2003

Testing And Modeling Electrical Characteristics Of Novel Silicon Carbide (Sic) Static Induction Transistors (Sits), Avinash S. Kashyap, Sharmila D. Mangan Lal, Ty R. Mcnutt, Alexander B. Lostetter, H. Alan Mantooth

Journal of the Arkansas Academy of Science

No abstract provided.


On The Area Of Hypercube Layouts, Ronald I. Greenberg, Lee Guan Sep 2002

On The Area Of Hypercube Layouts, Ronald I. Greenberg, Lee Guan

Computer Science: Faculty Publications and Other Works

This paper precisely analyzes the wire density and required area in standard styles for the hypercube. It shows that the most natural, regular layout of a hypercube of N^2 nodes in the plane, in a NxN grid arrangement, uses floor(2N/3)+1 horizontal wiring tracks for each row of nodes. (In the process, we see that the number of tracks per row can be reduced by 1 with a less regular design, as can also be seen from an independent argument of Bezrukov et al.) This paper also gives a simple formula for the wire density at any cut position and a …


Microdot - A Four-Bit Microcontroller Designed For Distributed Low-End Computing In Satellites, Anthony R. Woodcock Mar 2002

Microdot - A Four-Bit Microcontroller Designed For Distributed Low-End Computing In Satellites, Anthony R. Woodcock

Theses and Dissertations

Many satellites are an integrated collection of sensors and actuators that require dedicated real-time control. For single processor systems, additional sensors require an increase in computing power and speed to provide the multi-tasking capability needed to service each sensor. Faster processors cost more and consume more power, which taxes a satellite's power resources and may lead to shorter satellite lifetimes. An alternative design approach is a distributed network of small and low power microcontrollers designed for space that handle the computing requirements of each individual sensor and actuator. The design of microdot, a four-bit microcontroller for distributed low-end computing, is …


A Vhdl Implementation Of Bist Technique In Uart Design, Mohd. Yamani Idna Idris Jan 2002

A Vhdl Implementation Of Bist Technique In Uart Design, Mohd. Yamani Idna Idris

Student Works (2000-2009)

No abstract provided.


Microdot-A 4-Bit Synchronous Microcontroller For Space Applications, Kirby M. Watson Mar 2001

Microdot-A 4-Bit Synchronous Microcontroller For Space Applications, Kirby M. Watson

Theses and Dissertations

Satellites have limited power budgets due to the amount of power collected by the satellite's solar panels. The goal is to have a wide range of functionality, while running off a limited power source. Large microprocessors use large amounts of power to report back temperature and chemical sensor data to ground stations. By using small micro controllers to perform the data collection and minimizing the usage of the larger microprocessors, the satellites will save power. A prototype design of the Microdot 4-bit micro controller for space applications is presented. Requirements for the Microdot, such as microwatt power consumption and 23 …


Vhdl Implementation For Jawi Character Recognition, Mustafa Norita Adila Jan 2001

Vhdl Implementation For Jawi Character Recognition, Mustafa Norita Adila

Student Works (2000-2009)

Kewujudan tulisan jawi sejak dahulu lagi telah menghasilkan pelbagai karya penting dalam perkembangan islam. Sebagai satu bahasa pengantara, tulisan jawi dianggap penting dalam bidang penulisan. Tidak terhad hanya kepada buku-buku, dokumen-dokumen dan manuskrip-manuskrip yang ditulis dalam tulisan jawi, malah penggunaanya amat meluas dan meliputi keseluruhan bidang. Menyedari kepentingannya, timbul minat saya untuk mengkaji dengan lebih mendalam bagaimana komputer boleh mengenali dan memahami tulisan ini tanpa menggunakan tenaga manusia berdasarkan kepada beberapa kajian yang sedia ada yang telah dijalankan oleb mereka yang pakar dalam teknologi komputer digital. Secara keseluruhan, kajian ini akan membantu memudahkan lagi pengecaman tulisan tangan jawi yang dilakukan …


Rekabentuk Perkakasan Khas Ecc (Reed-Solomon), Muhamad Mursid Noorizan Jan 2001

Rekabentuk Perkakasan Khas Ecc (Reed-Solomon), Muhamad Mursid Noorizan

Student Works (2000-2009)

Dokumen ini disiapknn bagi menyediakan laporan tentang perjalanan projek perkakasan khas ECC yang dijalankan. Bahagian pertama dokumen ini terdapat pengenalan tentang projek. Bahagian kedua pula menyatakan tentang kajian yang telah dilakukan bagi memilih kod-kod pembetulan yang ingin dibangunkan. Seterusnya pada bahagian tiga, dinyatakan serba sedikit tentang bahasa yang digunakan dalam pembangunan projek iaitu VHDL. Sahagian keempat pula menceritakan tentang senibina-senibina dan rekabentuk-rekabentuk perkakasan khas. Dalam bahagian lima, dokumen menceritakan tentang fasa pembangunan yang telah dijalankan. Bahagian enam dan tujuh pula menceritakan tentang perbincangan dan kesimpulan daripada projek yang telah dijalankan.


Keyboard - Smart Card Reader Controller Using Vhdl, Lani Mohd Zuwairi Jan 2001

Keyboard - Smart Card Reader Controller Using Vhdl, Lani Mohd Zuwairi

Student Works (2000-2009)

As the time fly by the technology of computers has improves and much security is needed in every transaction of data that being done. In this project, designing a microcontroller for keyboard and smart card reader terminal integration is being done. At first stage, the architecture of the controller will analyze and studied. This will need some practice of knowledge in computer organization and architecture, as well as microprocessors architecture designs. Then the architecture is design using hardware prototyping. This is by using the VHSIC Hardware Description Language (VHDL). The codes done using the language then being simulate to get …


Mekanisma Pengujian Alu Menggunakan Teknik Boundary Scan, Abdul Aziz Ahmad Zaki Zamani Jan 2000

Mekanisma Pengujian Alu Menggunakan Teknik Boundary Scan, Abdul Aziz Ahmad Zaki Zamani

Student Works (2000-2009)

ALU testing mechanism using Boundary Scan technique is a project which is develop to be the tester for testing the digital circuit, integrated circuit and computer chip. The goal of this project is to develop a mechanism and as well building an ALU chip so that we will able to test and determine whether the chips are in a good shape and condition. This project contains two parts: one is lo develop an ALU and second is to develop the boundary scan chip. ALU is a unit or a component for a cligital circuit or a integrated circuit which is …


Litar Aritmetik Reja, Abd. Mutalib Leorna Shazerine Jan 2000

Litar Aritmetik Reja, Abd. Mutalib Leorna Shazerine

Student Works (2000-2009)

Projek Ilmiah Tahap Akhir II, iaitu WXES 3182 adalah suatu latihan akademik di dalam penyelidikan, rekabentuk, pembangunan dan komunikasi yang melibatkan prinsip-prinsip sains komputer. Projek WXES 3182 ini merupakan kursus pelengkap bagi pelajar-pelajar tahun akhir untuk mendapatkan penganugerahan Sarjana Muda Sains Komputer. Projek WXES 3182 ini adalah kesinabungan daripada projek WXES 3181 Kajian penyehdikan yang telah dijalankan adalah berkaitan dengan konsep sistem nombor reja dan litar aritmetik reja. Laporan latihan ilmiah tahap akhir II ini, merangkumi pembangunan projek WXES 3181 dan WXES 3182. laporan ini terdiri daripada lapan bahagian dan diantaranya ialah pengenalan kepada projek, kajian literasi, metodologi yang digunakan …


Vhdl Description For Ip Engine, Bathich Zeliall Jan 2000

Vhdl Description For Ip Engine, Bathich Zeliall

Student Works (2000-2009)

Developing hardware support for network layer protocol processing is a very complex and demanding task. However. for optimal performance hardware acceleration can be required. To cope with the situation. this project present a high-level design approach. which targets the development of configurable and reusable components. Therefore it obtains the integration of advanced tools for the development of the IP Engine into the design environment. This process is illustrated based on a TCP/IP header analysis and validation component for which initial performance results are presented. The development of this Engine is embedded in an approach to develop flexible and configurable protocol …


Pendarab Titik Apungan 32bit Bertalian Paip, Noorzaily Mohamed Noor Jan 2000

Pendarab Titik Apungan 32bit Bertalian Paip, Noorzaily Mohamed Noor

Student Works (2000-2009)

Tesis ini menghuraikan sebuah pendarab titik apungan 32bit bertalian paip 18MHz yang direkabentuk menggunakan bahasa perihalan perkakasan YHDL, peralatan sintesis Synopsys FPGA Express dan ·peralatan pemetaan Xilinx Alliance, PTA ini menggunakan 1007 CLB dan 100 10B di mana peranti pemetaan yang digunakan ialah xc4036xl-bg432-2 daripada pustaka XC4000 Xilinx FPGA. Pendarab ini mengandungi tiga tahap talian paip yang belainan fungsi. Tahap pertama melaksanakan penjanaan dedarab dan penambahan dedarab secara carry save dan penambahan eksponen. la menggunakan algoritma Booth tertib kedua dan pepohon Wallace dengan pemampat 4-2. Tahap kcdua pula melakukan penambahan bawaan rambatan akhir, penormalan mantisa dan pembetulan eksponen manakala tahap …


Approximation And Optimization Of An Auditory Model For Realization In Vlsi Hardware, Samuel L. Sangregory Dec 1999

Approximation And Optimization Of An Auditory Model For Realization In Vlsi Hardware, Samuel L. Sangregory

Theses and Dissertations

The Auditory Image Model (AIM) is a software tool set developed to functionally model the role of the ear in the human hearing process. AIM includes detailed filter equations for the major functional portions of the ear. Currently, AIM is run on a workstation and requires 10 to 100 times real-time to process audio information and produce an auditory image. An all-digital approximation of the AIM which is suitable for implementation in very large scale integrated circuits is presented. This document details the mathematical models of AIM and the approximations and optimizations used to simplify the filtering and signal processing …


Static Compaction Of Test Sequences For Synchronous Sequential Circuits, Lijie Qi Aug 1998

Static Compaction Of Test Sequences For Synchronous Sequential Circuits, Lijie Qi

Dissertations and Theses

Today, VLSI design has progressed to a stage where it needs to incorporate methods of testing circuits. The Automatic Test Pattern Generation (ATPG) is a very attractive method and feasible on almost any combinational and sequential circuit.

Currently available automatic test pattern generators (ATPGs) generate test sets that may be excessively long. Because a cost of testing depends on the test length, compaction techniques have been used to reduce that length. The motivation for studying test compaction is twofold. Firstly, by reducing the test sequence length, the memory requirements during the test application and the test application time are reduced. …


Gaas Implementation Of Fir Filter, Anup Savla Jan 1998

Gaas Implementation Of Fir Filter, Anup Savla

Theses : Honours

This thesis discusses the findings of the final year project involving Gallium Arsenide implementation of a triangular FIR filter to perform discrete wavelet transforms. The overall characteristics of Gallium Arsenide technology- its construction, behaviour and electrical charactersitics as they apply to VLSI technology - were investigated in this project. In depth understanding of its architecture is required to be able to understand the various design techniques employed. A comparison of Silicon and GaAs performance and other characteristics has also been made to fully justify the choice of this material for system implementation. A lot of research and active interest has …


Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih Feb 1997

Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih

Computer Science: Faculty Publications and Other Works

We give algorithms to minimize density for VLSI channel routing problems with terminals that are movable subject to certain constraints. The main cases considered are channels with linear order constraints, channels with linear order constraints and separation constraints, channels with movable modules containing fixed terminals, and channels with movable modules and terminals. In each case, we improve previous results for running time and space by a factor of L/\lgn and L, respectively, where L is the channel length, and n is the number of terminals.


Parallel Algorithms For Single-Layer Channel Routing, Ronald I. Greenberg, Shih-Chuan Hung, Jau-Der Shih Jan 1997

Parallel Algorithms For Single-Layer Channel Routing, Ronald I. Greenberg, Shih-Chuan Hung, Jau-Der Shih

Computer Science: Faculty Publications and Other Works

We provide efficient parallel algorithms for the minimum separation, offset range, and optimal offset problems for single-layer channel routing. We consider all the variations of these problems that are known to have linear- time sequential solutions rather than limiting attention to the "river-routing" context, where single-sided connections are disallowed. For the minimum separation problem, we obtain O(lgN) time on a CREW PRAM or O(lgN / lglgN) time on a (common) CRCW PRAM, both with optimal work (processor- time product) of O(N), where N is the number of terminals. For the offset range problem, we obtain the same time and processor …