VLSI and Circuits, Embedded and Hardware Systems Commons^™

Parameterizable Network-On-Chip Emulation Framework, Jaya Suseela

UNLV Theses, Dissertations, Professional Papers, and Capstones

Networks-on-Chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. But there is no public accessible HDL synthesizable NoC framework which connects industrial level cores and runs real applications on them. Moreover, many challenging research problems remain unsolved at all levels of design abstraction; design exploration of NoC architecture for applications, scheduling and mapping algorithms, evaluation of switching, topology or routing algorithm for efficient execution of application and optimizing communication cost, area, energy etc Solution to solve the above problem calls for the development of synthesizable, parameterizable NoC Framework that would evaluate and implement the above …

A Single-Chip Ultra-Wideband Based Wireless Sensor Network Node, Nathan R. Schemm

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

This dissertation presents the design of a next-generation wireless sensor network node. The node incorporates many new and innovative technologies such as an ultra-wideband radio which allows very low-energy communication, a low-power radiation detection front end, and an efficient implementation of dynamic voltage scaling which improves the energy efficiency of the integrated processor. The complete design is integrated on a single chip for maximum power savings and minimal size.

The ultra-wideband transceiver includes many novel techniques to produce a receiver with low power consumption and fast and accurate packet acquisition and reception. These include the use of a standard symmetric …

Asynchronous Mips Processors: Educational Simulations, Robert L. Webb

Master's Theses

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …

Synthesizing Optimal Fixed-Point Arithmetic For Embedded Signal Processing, Kenneth J. Hass

Faculty Conference Papers and Presentations

No abstract provided.

Polyenvi, Stephen Beard, Josh Engel, Paul Fake, Diego Flores, Alvaro Nunez, Miguel Wong

Electrical Engineering

Poor indoor air quality is a problem that is recognized by the Environmental Protection Agency (EPA) to cause health issues. In order to raise awareness of this problem, this document outlines the construction of a device that economically measures air quality through five metrics: dust, smoke, ozone, humidity, and temperature. The device integrates with a router to provide users access to information about their indoor air quality anywhere over the internet as well as local access to the data via an LCD mounted on the router. By increasing indoor air quality awareness, this device will aid users in making adjustments …

K-Delta-1-Sigma Modulators For Wideband Analog-To-Digital Conversion, Vishal Saxena

Boise State University Theses and Dissertations

As CMOS technology scales, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents, and additional mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in these small processes a first-order K-Delta-1-Sigma (KD1S) modulator-based ADC was proposed. The KD1S topology employs inherent time-interleaving with a shared integrator and K-quantizing feedback paths and can potentially achieve significantly higher conversion bandwidths when compared to the traditional …

Global Positioning Logger, Matthew Hall

Computer Engineering

The Global Positioning Logger (GPL) is a mobile embedded device that utilizes GPS technology. The GPS data is used to display current speed and past global locations.

Design Techniques To Improve Time Dependent Dielectric Breakdown Based Failure For Cmos Circuits, Emanuel S. Tarog

Master's Theses

This project investigates the failure of various CMOS circuits as a result of Time Dependent Dielectric Breakdown (TDDB) and explores design techniques to increase the mean time to failure (MTTF) of large-scale circuits. Time Dependent Dielectric Breakdown is a phenomenon where the oxide underneath the gate degrades as a result of the electric field in the material. Currently, there are few well documented design techniques that can increase lifetime, but with a tool chain I created called the MTTF Analyzing Program, or MAP, I was able to test circuits under various conditions in order to identify weak links, discover relationships, …