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- Fat-trees (2)
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Articles 1 - 5 of 5
Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems
Efficient Interconnection Schemes For Vlsi And Parallel Computation, Ronald I. Greenberg
Efficient Interconnection Schemes For Vlsi And Parallel Computation, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
This thesis is primarily concerned with two problems of interconnecting components in VLSI technologies. In the first case, the goal is to construct efficient interconnection networks for general-purpose parallel computers. The second problem is a more specialized problem in the design of VLSI chips, namely multilayer channel routing. In addition, a final part of this thesis provides lower bounds on the area required for VLSI implementations of finite-state machines. This thesis shows that networks based on Leiserson's fat-tree architecture are nearly as good as any network built in a comparable amount of physical space. It shows that these "universal" networks …
Efficient Multi-Layer Channel Routing, Ronald I. Greenberg
Efficient Multi-Layer Channel Routing, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
No abstract provided.
Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson
Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson
Computer Science: Faculty Publications and Other Works
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda + lg n lg lg n) with probability 1-O(1/n). The best previous …
Lower Bounds On The Area Of Finite-State Machines, M. J. Foster, Ronald I. Greenberg
Lower Bounds On The Area Of Finite-State Machines, M. J. Foster, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
There are certain straightforward algorithms for laying out finite-state machines. This paper shows that these algorithm are optimal in the worst case for machines with fixed alphabets. That is, for any s and k, there is a deterministic finite-state machine with s states and k symbols such that any layout algorithm requires Ω(ks log s) area to lay out its realization. Similarly, any layout algorithm requires Ω(ks^2) area in the worst case for nondeterministic finite-state machines with s states and k symbols.
Versatile Potentiostat With Optional Computer Control, Gary L. Fuller, William A. Russell Jr., Roger M. Hawk, James D. Wilson, P. D. Bratton
Versatile Potentiostat With Optional Computer Control, Gary L. Fuller, William A. Russell Jr., Roger M. Hawk, James D. Wilson, P. D. Bratton
Journal of the Arkansas Academy of Science
A versatile potentiostat which can supply a maximum of 125 ma is described. The potentiostat uses readily available electronic components and an interface is detailed which allows the potentiostat optional computer control.