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Articles 1 - 18 of 18
Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems
An Rf Cmos Implementation Of An Adaptive Filter For Narrow-Band Interferer Suppression In Uwb Systems, Markus Both
An Rf Cmos Implementation Of An Adaptive Filter For Narrow-Band Interferer Suppression In Uwb Systems, Markus Both
Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research
Ultra-wideband (UWB) technology is a new type of technology for wireless communication that is based on the transmission of low power sub-nanosecond pulses. UWB communication utilizes a large bandwidth that overlaps and is coexistent with other wireless communication standards that can be also considered as narrow-band interferers. Because UWB systems are highly susceptible to narrow-band interferers, there is a demand for interferer suppression. An adaptive filter consisting of a two-element diversity receiver that performs minimum mean square error combining (MMSE) by the LMS algorithm is proposed. Thereby the elements of the LMS algorithm as well as the receiver LNA were …
Modeling Of Sic P-Channel Insulated Gate Bipolar Transistors (Igbts), Mahmood Saadeh
Modeling Of Sic P-Channel Insulated Gate Bipolar Transistors (Igbts), Mahmood Saadeh
Graduate Theses and Dissertations
A new physics-based IGBT compact model has been developed for circuit simulation of silicon (Si) or silicon carbide (SiC) devices. The model accurately predicts the steady-state output, transfer and switching characteristics of the IGBT under a variety of different conditions. This is the first IGBT model to predict the behavior of p-channel SiC IGBTs. Previous work on IGBT models has focused on Si n-channel IGBTs [1-3]. This unified model is not limited to SiC p-channel IGBTs; the user has the option to select between Si or SiC, and n-channel or p-channel, making it the first IGBT model that captures the …
An Inertial Measurement System For Hand And Finger Tracking, Edward Nelson Henderson
An Inertial Measurement System For Hand And Finger Tracking, Edward Nelson Henderson
Boise State University Theses and Dissertations
The primary Human Computer Interfaces (HCI) today are the keyboard and mouse. These interfaces do not facilitate a fluid flow of thought and intent from the operator to the computer. A computer mouse provides only 2 Degrees of Freedom (2DOF). Touch interfaces also provide 2DOF, but with multiple points, making the touch interface far more expressive. The hand has 6 Degrees of Freedom (6DOF)by itself. Combined with the motion of the fingers, the hand has the potential to represent a vast array of differing gestures. Hand gestures must be captured before they can be used as a HCI. Fortunately, advances …
Auto-Tuning Antenna, John Chen, Jennifer Tighe
Auto-Tuning Antenna, John Chen, Jennifer Tighe
Electrical Engineering
Radio transmitters and antennas have differing impedances at the output and feedpoint, depending on frequency. Modern antenna tuning methods involve manual or automatic resistance and reactance network adjustment to match transmitter and antenna impedance. This reduces power reflections to the transmitter, but introduces losses and prevents full transmitter power from being radiated at the antenna. This project utilizes a variable length antenna element to tune and match transmitter and antenna impedances, allowing efficient power transfer to the antenna. The antenna length varies from 0 to 30.5 inches. The method involves an RF signal with a maximum power of 2 watts …
A 2-D Processor Array For Massively Parallel Image Processing, Anantha Krishna Nelliparthi
A 2-D Processor Array For Massively Parallel Image Processing, Anantha Krishna Nelliparthi
Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research
The concept of introducing image processing logic within the spatial gaps of an array of photodiodes is the key factor behind the presented work. A two-dimensional massively parallel image processing paradigm based on 8X8 pixel neighborhood digital processors has been designed. A low complexity processor array architecture along with its instruction set has been designed and fully verified on a FPGA platform. Various image processing tests have been run on the FPGA platform to demonstrate the functionality of a design that uses 12 parallel processors. The test results indicate that the architecture is scalable to support high frame rates while …
Investigation Of A Floating Load Buck Dc-Dc Switching Converter, Hong Tan
Investigation Of A Floating Load Buck Dc-Dc Switching Converter, Hong Tan
Graduate Theses and Dissertations
A floating load buck DC-DC switching converter was analyzed, simulated, designed and prototyped. The floating load buck converter is first compared to the conventional buck converter. It was found that both the floating load buck converter and conventional buck converter exhibit similar conversion characteristics despite the differences in the placement of their output inductors. A floating load buck converter was designed to be used as a high-voltage off-line light-emitting diodes (LEDs) driver using a Texas Instruments' TPS92001 controller. Finally, the characteristics of this floating load buck converter LED driver were experimentally examined.
Full Custom Vlsi Design Of On-Line Stability Checkers, Chris Y. Lee
Full Custom Vlsi Design Of On-Line Stability Checkers, Chris Y. Lee
Master's Theses
A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.
A method for concurrent fault testing called On-line Stability Checking …
Wireless Embedded Smart Cameras: Performance Analysis And Their Application To Fall Detection For Eldercare., Alvaro Pinto
Wireless Embedded Smart Cameras: Performance Analysis And Their Application To Fall Detection For Eldercare., Alvaro Pinto
Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research
Wireless Embedded Smart Camera Networks has received a lot of attention from academia and industry because they are small in size and easy to deploy, and they offer a multitude of attractive applications. They can be used for embedded single unit applications, or can be networked for multi-camera applications.
We first analyze three different operation scenarios for a wireless vision sensor network wherein different levels of local processing is performed. A detailed quantitative comparison of three operation scenarios are presented in terms of energy consumption and latency. This quantitative analysis provides the motivation for performing high-level local processing and decision …
Discrete Alarm Clock, Travis Moore, Collin Barth
Discrete Alarm Clock, Travis Moore, Collin Barth
Electrical Engineering
The standard alarm clock, as used daily by millions worldwide, has clear room for modification and improvement. This paper documents an implementation that rectifies many of these flaws. Improvements include adjustable snooze length, an IR remote for ease of use, and an RF headset for discrete alarm use or potential incorporation into a device much like a hearing aid. The processes involved in creating a digital alarm clock, as well as the obstacles met in the implementation of the enhanced design, are detailed within.
Mp3 Player System Design, Eric Wu
Mp3 Player System Design, Eric Wu
Electrical Engineering
The purpose of this project is to design and build a portable audio player that reads music files off an SD card, decodes the music file and outputs the music through a headphone jack. A microcontroller running FreeRTOS will facilitate the data transfer between an SD card and the decoding chip. The decoded audio will then be sent to a high-end DAC chip that outputs the sound.
Laser Cursor, Michael Liman
Laser Cursor, Michael Liman
Electrical Engineering
A user controls a cursor on a computer screen using a laser pointer. A camera picks up the laser pointer’s position and sends the data to the computer to move the cursor in the correct position.
Controller Board Prototype Development For The Cal Poly Super Project, Clifford Susa
Controller Board Prototype Development For The Cal Poly Super Project, Clifford Susa
Electrical Engineering
Now in phase two of development, the Cal Poly Sustainable Power for Electrical Reources (SuPER) project will provide power to families for an estimated lifespan of 20 years at a cost of $500. Phase two of the SuPER project looks at implementing microcontrollers to monitor the health and status of the system. This senior project looks specifically at the performances of the SuPER Controller which communicates with the SuPER Digitizer to gather data such as voltage, current, temperature, and power. An SD memory card will store this data, and to view this data, then download to a PC.
Project 308: Augmented Reality Mario Kart, Joseph Abad, David Allender, Joryl Calizo, Ryan Gaspar, Gavin Lee
Project 308: Augmented Reality Mario Kart, Joseph Abad, David Allender, Joryl Calizo, Ryan Gaspar, Gavin Lee
Computer Engineering
Mario Kart is a popular go-kart racing game developed by Nintendo. The premise of the game is simple: drive a go-kart along a racetrack and reach the finish line before the other players. What makes this game unique, however, is the inclusion of weapons, traps, and other projectiles that a player can use to gain an advantage in the race. We have taken on the challenge of not only recreating this amazing game, but using the art of Augmented Reality to fully immerse the player in the full experience. Rather than play the game on a television screen with a …
Low-Power, High-Bandwidth And Ultra-Small Memory Module Design, Qawi Ibnzayd Harvard
Low-Power, High-Bandwidth And Ultra-Small Memory Module Design, Qawi Ibnzayd Harvard
Boise State University Theses and Dissertations
The main memory subsystem has become inefficient. The performance gained has come at the expenses of power consumption, capacity, and cost. This dissertation proposes novel module, DRAM, and interconnect architectures in an attempt to alleviate these trends. The proposed architectures utilize low-cost interconnects and packaging innovations to substantially reduce the power, and increase the capacity and bandwidth of the main memory system.
This dissertation develops the theory behind a low-cost packaging technology to create an 8-die and 32-die memory module. The 32-die memory module measures less than 2 cm3.
This dissertation also proposes a 4 Gb DRAM architecture …
Increasing Efficiency In Boundary Security With Wireless Sensor Networks And Geospatial Information Systems Using Homology Theory, Luis Berumen^, Eric Chaidez^, Hamide Dogan*, Jose Gerardo Rosiles**
Increasing Efficiency In Boundary Security With Wireless Sensor Networks And Geospatial Information Systems Using Homology Theory, Luis Berumen^, Eric Chaidez^, Hamide Dogan*, Jose Gerardo Rosiles**
COURI Symposium Abstracts, Spring 2011
As part of an institutional investigation, we attempt to address the challenges the US customs and Border protection agency faces in the El Paso region. Our research focuses on defining a system for the surveillance application, and the use of mathematical models employed to achieve a greater efficiency of such architecture. With the use of the defined system, we apply homology theory through the algebraic process of topology, to accomplish an independent coordinate-free based system, which covers the surveillance area, with lesser quantity of sensor nodes. Our architecture makes the use of an operating system for wireless sensor networks; TinyOS, …
Dynamic Polymorphic Reconfiguration To Effectively “Cloak” A Circuit’S Function, Jeffrey L. Falkinburg
Dynamic Polymorphic Reconfiguration To Effectively “Cloak” A Circuit’S Function, Jeffrey L. Falkinburg
Theses and Dissertations
Today's society has become more dependent on the integrity and protection of digital information used in daily transactions resulting in an ever increasing need for information security. Additionally, the need for faster and more secure cryptographic algorithms to provide this information security has become paramount. Hardware implementations of cryptographic algorithms provide the necessary increase in throughput, but at a cost of leaking critical information. Side Channel Analysis (SCA) attacks allow an attacker to exploit the regular and predictable power signatures leaked by cryptographic functions used in algorithms such as RSA. In this research the focus on a means to counteract …
Evaluation Of The Single Keybit Template Attack, Eric W. Garcia
Evaluation Of The Single Keybit Template Attack, Eric W. Garcia
Theses and Dissertations
Side Channel leakage is a serious threat to secure devices. Cryptographic information extraction is possible after examining any one of the various side channels, including electromagnetic. This work contributes a new method to achieve such a purpose. The Single Keybit Template Attack (SKTA) is introduced as a means to extract encryption keys from embedded processors and other integrated circuit devices performing DES encryptions by passively monitoring and exploiting unintentional RF emissions. Key extraction is accomplished by creating two templates for each bit value of the key based on instantaneous amplitude responses as a device executes DES operations. The resultant templates …
Multicore, Multithreaded, Phase-Synchronous Fm Sound Synthesizer, Justin Tomlin
Multicore, Multithreaded, Phase-Synchronous Fm Sound Synthesizer, Justin Tomlin
Electrical Engineering
This project implements a phase-synchronous FM synthesis algorithm in hardware. Envelope and low frequency oscillator modulation of oscillator parameters is implemented. The microcontroller the system is based on, the XMOS XS1-G4, allows for physical parallelism including features such as multiple cores, multiple hardware threads on each core, a hardware event-driven thread scheduler, and channel, channel ends, and link switches for thread and core communication. The event-driven architecture of this device was ideal for implementing this synthesis algorithm. The final product is portable, durable, has a simple, intuitive user interface, and allows for extensive spectral shaping capabilities. The basic functional requirements …