VLSI and Circuits, Embedded and Hardware Systems Commons^™

Fast And Accurate Automatic Design Of Spiral Inductors From High-Level Specification, Heba Ismail

Theses and Dissertations

Integrated on-chip planar spiral inductors are widely employed in communication circuit blocks and other various electronic devices, thus becoming an essential passive component of RF integrated circuits (RFICs). A common vital spiral inductor design problem is determining the optimum layout parameters of spiral inductors that yield the desired inductance value and achieve highest quality factor at the intended operating frequency. Various approaches tackle this difficulty, but the most prevalent approaches for designing inductors are using an electromagnetic simulator or a library of pre-designed inductors. The latter approach requires an extensive amount of time and computational resources, whereas the former restricts …

Physical Effects On The Worst-Case Delay Analysis And Signal Integrity Of Buses And Spirals, Mahmoud Mahany

Theses and Dissertations

Physical effects have a significant impact on the IC design which will be investigated in this thesis. Moving toward advanced technology nodes, magnetic effects become more dominant than capacitive effects. As the dimensions of the devices go down and the interconnect manipulates the circuit behavior more and more. Cross talking and voltage drops are affecting the design heavily, however - going to the full electromagnetic point of view - current return path (CRP) adds significant parasitics to the performance of the chip. Neglecting the CRP gives wrong intuition and simulation of the designs, especially that the environment and surroundings can …

Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya

Theses and Dissertations

High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a …

Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad

Theses and Dissertations

Running computer vision algorithms requires complex devices with lots of computing power, these types of devices are not well suited for space deployment. The harsh radiation environment and limited power budgets have hindered the ability of running advanced computer vision algorithms in space. This problem makes running an on-orbit servicing detection algorithm very difficult. This work proposes using a low powered FPGA to accelerate the computer vision algorithms that enable satellite component feature extraction. This work uses AMD/Xilinx’s Zynq SoC and DPU IP to run model inference. Experiments in this work centered around improving model post processing by creating implementations …

Development Of The Subwave Rov And Neural-Inertial Positioning System, Jason Farmer

Theses and Dissertations

This report documents the development of the Subwave, a remotely-operated underwater vehicle (ROV), and an artificial neural network based inertial positioning system. The Subwave uses the open-source ArduSub software framework, commercial-off-the-shelf hardware components, and several custom systems. It is designed as a platform for researching autonomous underwater vehicles (AUVs). The first step for an AUV is navigating waypoints, which requires the AUV to know its global position. Since global navigation satellite systems (GNSSs) are denied underwater, the available underwater positioning systems were surveyed and determined that all the available systems were too large and expensive for the Subwave. It was …

Machine Learning Applications To Static Timing Analysis, Waseem Mohamed Raslan

Theses and Dissertations

Modeling complex cell behavior is critical for accurate static timing analysis. Effective current source model, ECSM, and composite current source, CCS, waveform data compression became a necessity to reduce the size of technology files and increase the accuracy of the cell characterization data. We used deep learning nonlinear Autoencoders to compress voltage and current waveforms and compared them with singular value decomposition, SVD, approach. Autoencoders gave ~1.67x compression ratio for voltage waveforms better than SVD approach and gave 45x to 55x better compression ratio compared to other lossless techniques like bz2 and gzip. Autoencoders achieved ~1.7x compression ratio for complex …

Integrated Circuits Parasitic Capacitance Extraction Using Machine Learning And Its Application To Layout Optimization, Mohamed Saleh Abouelyazid Saleh

Theses and Dissertations

The impact of parasitic elements on the overall circuit performance keeps increasing from one technology generation to the next. In advanced process nodes, the parasitic effects dominate the overall circuit performance. As a result, the accuracy requirements of parasitic extraction processes significantly increased, especially for parasitic capacitance extraction. Existing parasitic capacitance extraction tools face many challenges to cope with such new accuracy requirements that are set by semiconductor foundries (< 5% error). Although field-solver methods can meet such requirements, they are very slow and have a limited capacity. The other alternative is the rule-based parasitic capacitance extraction methods, which are faster and have a high capacity; however, they cannot consistently provide good accuracy as they use a pre-characterized library of capacitance formulas that cover a limited number of layout patterns. On the other hand, the new parasitic extraction accuracy requirements also added more challenges on existing parasitic-aware routing optimization methods, where simplified parasitic models are used to optimize layouts.

This dissertation provides new solutions for interconnect parasitic capacitance extraction and parasitic-aware routing optimization methodologies in order to cope with the new accuracy requirements of advanced process nodes as follows. …

Single Event Transient Sensitivity Measurement And Worst-Case Test Vector Exploration For Asic Devices Exposed To Space Single Event Environment, Mohamed Wael

Theses and Dissertations

Space radiation and nuclear reactors produce single event effects (SEE) in electronic circuits and impact their performance. The SEE phenomena cause circuits and electronic devices to fail by producing faulty results. Therefore, today’s circuit’s reliability is a significant concern for all circuit designers.

This thesis suggests a new automated flow to measure the single-event-transient (SET) effects in combinational circuits in application-specific integrated circuits (ASIC) while reaching full fault coverage. The developed flow characterizes the whole circuit nodes by identifying the most sensitive paths to the propagated SET pulses from the node under test to an observable primary output, causing single …

Fault Modeling And Test Vector Generation For Asic Devices Exposed To Space Single Event Environment, Ahmed Mohamed

Theses and Dissertations

This work aims at providing a concise automated flow to predict the effect of Single Event Transients (SETs) on ASIC chips by developing a method to characterize the circuit susceptibility to SET pulses propagation and then generation of the required input vectors that sensitize the victim paths. A new enhanced method for SET electrical propagation modeling is proposed and compared to a previously published analytical model. The method was applied on different standard cells libraries built over XFAB Xh018 technology and verified for accuracy against simulations. The new method showed enhancement in accuracy compared with previous work in literature. Industrial …

Systematic Model-Based Design Assurance And Property-Based Fault Injection For Safety Critical Digital Systems, Athira Varma Jayakumar

Theses and Dissertations

With advances in sensing, wireless communications, computing, control, and automation technologies, we are witnessing the rapid uptake of Cyber-Physical Systems across many applications including connected vehicles, healthcare, energy, manufacturing, smart homes etc. Many of these applications are safety-critical in nature and they depend on the correct and safe execution of software and hardware that are intrinsically subject to faults. These faults can be design faults (Software Faults, Specification faults, etc.) or physically occurring faults (hardware failures, Single-event-upsets, etc.). Both types of faults must be addressed during the design and development of these critical systems. Several safety-critical industries have widely adopted …

Toward Biologically-Inspired Self-Healing, Resilient Architectures For Digital Instrumentation And Control Systems And Embedded Devices, Shawkat Sabah Khairullah

Theses and Dissertations

Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes. One of the more essential concepts for achieving this goal is the notion of resilient and survivable digital I&C systems. In recent years, self-healing concepts based on biological physiology have received attention for the design of robust digital systems. However, many of these approaches have not been architected from the outset with safety in mind, nor have they been targeted for the automation community where a significant need exists. This dissertation presents a new self-healing digital …

A Hierarchical Architectural Framework For Securing Unmanned Aerial Systems, Matthew Leccadito

Theses and Dissertations

Unmanned Aerial Systems (UAS) are becoming more widely used in the new era of evolving technology; increasing performance while decreasing size, weight, and cost. A UAS equipped with a Flight Control System (FCS) that can be used to fly semi- or fully-autonomous is a prime example of a Cyber Physical and Safety Critical system. Current Cyber-Physical defenses against malicious attacks are structured around security standards for best practices involving the development of protocols and the digital software implementation. Thus far, few attempts have been made to embed security into the architecture of the system considering security as a holistic problem. …

Implementation And Performance Of Factorized Backprojection On Low-Cost Commercial-Off-The-Shelf Hardware, Alec C. Rasmussen

Theses and Dissertations

Traditional Synthetic Aperture Radar (SAR) systems are large, complex, and expensive platforms that require significant resources to operate. The size and cost of the platforms limits the potential uses of SAR to strategic level intelligence gathering or large budget research efforts. The purpose of this thesis is to implement the factorized backprojection SAR image processing algorithm in the C++ programming language and test the code's performance on a low cost, low size, weight, and power (SWAP) computer: a Raspberry Pi Model B. For a comparison of performance, a baseline implementation of filtered backprojection is adapted to C++ from pre-existing MATLAB® …

An Openeaagles Framework Extension For Hardware-In-The-Loop Swarm Simulation, Derek B. Worth

Theses and Dissertations

Unmanned Aerial Vehicle (UAV) swarm applications, algorithms, and control strategies have experienced steady growth and development over the past 15 years. Yet, to this day, most swarm development efforts have gone untested and thus unimplemented. Cost of aircraft systems, government imposed airspace restrictions, and the lack of adequate modeling and simulation tools are some of the major inhibitors to successful swarm implementation. This thesis examines how the OpenEaagles simulation framework can be extended to bridge this gap. This research aims to utilize Hardware-in-the-Loop (HIL) simulation to provide developers a functional capability to develop and test the behaviors of scalable and …

Dynamic Polymorphic Reconfiguration To Effectively “Cloak” A Circuit’S Function, Jeffrey L. Falkinburg

Theses and Dissertations

Today's society has become more dependent on the integrity and protection of digital information used in daily transactions resulting in an ever increasing need for information security. Additionally, the need for faster and more secure cryptographic algorithms to provide this information security has become paramount. Hardware implementations of cryptographic algorithms provide the necessary increase in throughput, but at a cost of leaking critical information. Side Channel Analysis (SCA) attacks allow an attacker to exploit the regular and predictable power signatures leaked by cryptographic functions used in algorithms such as RSA. In this research the focus on a means to counteract …

Evaluation Of The Single Keybit Template Attack, Eric W. Garcia

Theses and Dissertations

Side Channel leakage is a serious threat to secure devices. Cryptographic information extraction is possible after examining any one of the various side channels, including electromagnetic. This work contributes a new method to achieve such a purpose. The Single Keybit Template Attack (SKTA) is introduced as a means to extract encryption keys from embedded processors and other integrated circuit devices performing DES encryptions by passively monitoring and exploiting unintentional RF emissions. Key extraction is accomplished by creating two templates for each bit value of the key based on instantaneous amplitude responses as a device executes DES operations. The resultant templates …

Removing Redundant Logic Pathways In Polymorphic Circuits, Hanseok Kim

Theses and Dissertations

Evaluating the quality of software and circuit obfuscators is a research goal of great interest. However, there exists little research about evaluation of obfuscation effectiveness through analyzing and investigating redundancies found in the obfuscated variants. In this research, we consider programs represented as structural combinational circuits and then analyze obfuscated variants of those circuits through a tool that produces functionally equivalent variants based on subcircuit selection and replacement. We then consider how Boolean logic and reduction affects the size and levelization of circuit variants, giving us a concrete metric by which to consider obfuscation effectiveness. To accomplish these goals, we …

A Modular Mixed Signal Vlsi Design Approach For Digital Radar Applications, Brian M. Brakus

Theses and Dissertations

This study explores the idea of building a library of VHDL configurable components for use in digital radar applications. Configurable components allows a designer to choose which components he or she needs and configures those components for a specific application. By doing this, design time for ASICs and FPGAs is shortened because the components are already designed and tested. This idea is demonstrated with a configurable dynamic pipelinable fast fourier transform. Many FFT implementations exist, but this implementation is both configurable and dynamic. Pre-synthesis customization allows the FFT to be tailored to almost any DSP application, and the dynamic property …

Microdot - A Four-Bit Microcontroller Designed For Distributed Low-End Computing In Satellites, Anthony R. Woodcock

Theses and Dissertations

Many satellites are an integrated collection of sensors and actuators that require dedicated real-time control. For single processor systems, additional sensors require an increase in computing power and speed to provide the multi-tasking capability needed to service each sensor. Faster processors cost more and consume more power, which taxes a satellite's power resources and may lead to shorter satellite lifetimes. An alternative design approach is a distributed network of small and low power microcontrollers designed for space that handle the computing requirements of each individual sensor and actuator. The design of microdot, a four-bit microcontroller for distributed low-end computing, is …

Microdot-A 4-Bit Synchronous Microcontroller For Space Applications, Kirby M. Watson

Theses and Dissertations

Satellites have limited power budgets due to the amount of power collected by the satellite's solar panels. The goal is to have a wide range of functionality, while running off a limited power source. Large microprocessors use large amounts of power to report back temperature and chemical sensor data to ground stations. By using small micro controllers to perform the data collection and minimizing the usage of the larger microprocessors, the satellites will save power. A prototype design of the Microdot 4-bit micro controller for space applications is presented. Requirements for the Microdot, such as microwatt power consumption and 23 …

Approximation And Optimization Of An Auditory Model For Realization In Vlsi Hardware, Samuel L. Sangregory

Theses and Dissertations

The Auditory Image Model (AIM) is a software tool set developed to functionally model the role of the ear in the human hearing process. AIM includes detailed filter equations for the major functional portions of the ear. Currently, AIM is run on a workstation and requires 10 to 100 times real-time to process audio information and produce an auditory image. An all-digital approximation of the AIM which is suitable for implementation in very large scale integrated circuits is presented. This document details the mathematical models of AIM and the approximations and optimizations used to simplify the filtering and signal processing …

Accelerating Conservative Parallel Simulation Of Vhdl Circuits, Joel F. Hurford

Theses and Dissertations

This research effort considers heuristic and cost model based techniques for the optimal partitioning of VHDL circuits for parallel simulation. Correlation statistics are gathered on a wide variety of graph-based a priori parameters. Linear regression is used to identify significant parameters for inclusion in a representative cost model. Driving a greedy search, this cost model is used to improve upon initial heuristic partitions. The influence of feedback dominated previous research so a no-feedback algorithm is used to create the initial partition The circuits studied range from 1,050 to 4,243 gates.

Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp

Theses and Dissertations

Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural …

A Physics-Based Heterojunction Bipolar Transistor Model For Integrated Circuit Simulation, James A. Fellows

Theses and Dissertations

The purpose of this research effort was to derive a physics-based dc model for a Heterojunction Bipolar Transistor HBT. The dc model was then linearized to arrive at a small-signal model that accurately predicts the devices electrical behavior at microwave frequencies. This new model offers features not found in previous analytical or physics-based HBT models such as consideration of a cylindrical emitter-base geometry and is direct implementation into SPICE Simulation Program with Integrated Circuit Emphasis. The device model parameters were determined from a knowledge of the device material, geometry, and fabrication process. The model was then developed by using semiconductor …

Version And Transaction Management In Osmagic: An Object-Oriented Database Implementation Of The Magic Vlsi Layout Design Tool, Gary M. Lightner

Theses and Dissertations

The goal of this thesis was to study the feasibility of using an object-oriented database management system to provide the functionality and performance needed to support a complex computer-aided design tool. We do this by modifying OSMagic, a prototype system of the Magic very large scale integrated (VLSI) circuit design tool implemented on the ObjectStore object- oriented database management system. OSMagic was changed to support three different interfaces to ObjectStore and to work in a networking environment. We then designed and examined the use of version and transaction management models as a means of addressing the weaknesses of the prototype …

A Generic Template Extractor (Gentex) In C For Vlsi Design Verification, Kenneth J. Mcclellan Jr.

Theses and Dissertations

The problem of VLSI design verification through circuit extraction was analyzed. The problems of creating a simple template format, the permutability of pins, maintaining connectivity, and performance were focused on. A generic template extractor (GENTEX) was developed in the C programming language for use as a testbed to find solutions to these problems. Six different extraction algorithms were tested with GENTEX and compared based on performance. EDIF translation programs were used to interface with GENTEX on both the input and output sides. One translation program converted an EDIF representation of a schematic into the template format used by GENTEX. The …

Design And Development Of A High-Speed Winograd Fast Fourier Transform Processor Board, James F. Herron

Theses and Dissertations

Since 1985, the Air Force Institute of Technology has pursued a project to develop a 4080-point Discrete Fourier Transform processor using the Winograd Fourier Transform Algorithm (WFTA) and Good-Thomas Prime Factoring Algorithm (PFA). In the first attempt to build a working system, this research effort designed and constructed, in part, a modified single processor architecture in order to demonstrate the proof of concept of the WFTA system design. This prototype architecture is simpler in implementation but uses the same principles and procedures as those of the 4080-point WFTA design. The design developed in this thesis was validated using the Very …

Experimental Evaluation Of Incorporating Digital And Analog Integrated Circuit Die On A Common Substrate Utilizing Silicon-Hybrid Wafer-Scale Integration Technology, Philip C. Reamy

Theses and Dissertations

The objective of this research effort was to investigate the implementation of analog circuits in a wafer scale integration system. A test circuit composed of analog and digital subsystems was designed and tested through simulation. IC die containing this test circuit were utilized in the WSI system fabrication. Preliminary investigations were conducted to evaluate the potential improvements to the IC die mounting procedure, a key step in fabricating functional WSI systems. These investigations demonstrated a procedure which produced repeatable results in achieving acceptable planarization of IC die and host substrate surfaces. These investigations also demonstrated the successful application of a …

Hardware-Verification Through Logic Extraction, Michael A. Dukes

Theses and Dissertations

A Prolog-based system is described which employs logic-extraction to perform hardware-verification. The extraction rules are built automatically from hierarchical structural VHDL models, enabling the equivalence of a structural VHDL description and a layout specification to be verified. Pin-to-pin critical- path analysis is performed within the logic-extraction process; many noncritical paths are pruned early, making pin-to-pin critical path analysis of large circuits feasible. It is demonstrated that a design methodology based on logic extraction, VHDL, and a layout tool can provide a fabricated functionally- correct IC design without circuit-level or switch-level simulation. This methodology is shown to be practical for VLSI …

Design And Analysis Of Electrical Circuits That Produce Fractional-Order Differentiation, Richard N. Hughes

Theses and Dissertations

Two half-order differentiator circuit designs were investigated and their electrical performance evaluated (Oldham and Oldfield). Initially, each circuit design was computer modelled and simulated using the HSPICE computer analysis program. Then, each circuit design (Oldham and Oldfield) was fabricated with two different component technologies. This resulted in four circuits, realized on printed circuit boards, to be evaluated--Oldham discrete component; Oldham hybrid component; Oldfield discrete component; and Oldfield surface mount component. The characterizations of each circuit's electrical performance is documented with time, phase, gain, noise and spectrum responses. A comparison of each circuit's performance versus the design criteria and computer model …