VLSI and Circuits, Embedded and Hardware Systems Commons^™

Optimization And Acceleration Of Puf Design Through Reduced Order Standard Cell Modeling, Ian Z. Wilcox

Electrical and Computer Engineering ETDs

Application Specific Integrated Circuit (ASIC) designs continue to scale with ever increasing complexity and device counts in the billions. Demand for scalable high-fidelity simulations of these systems drives the need for the development of novel modeling capabilities. This research formulates a non-intrusive model order reduc-tion (MOR) framework, called PUF-ROMS, to accelerate and optimize the design and analysis of physical unclonable functions (PUFs) on ASICs. The primary goals of PUF-ROMS are to estimate entropy and temperature-voltage noise (TV-noise) of circuit structures used in the design in an accelerated evaluation environment to enable designers to explore architecture options with the goal of …

Design Of A Subthreshold Cmos Inverter-Based Amplifier For Low-Noise And Low-Power Applications, Landon Alexander Schmucker

Electrical and Computer Engineering ETDs

Amplification is a fundamental function in most analog circuits. There is a fast-growing demand for low-power, low-noise, and high-gain amplifiers. Modern semiconductor processes are increasingly optimized for digital applications, which has introduced new challenges in analog design. To address these challenges, analog designers have investigated replacing conventional analog circuits with digital implementations. One promising application is the typical CMOS inverter as an amplifier.

This research presents a CMOS inverter-based amplifier with feedback designed to achieve low power consumption, low input noise, and high gain. Unlike typical CMOS inverter-based amplifiers, this topology has two distinctive features: (1) it uses a MOSFET …

Fail-Safe Logic Design Strategies Within Modern Fpga Architectures, Priya A. Bhakta

Electrical and Computer Engineering ETDs

Field Programmable Gate Arrays (FPGAs) are vulnerable to radiation-induced single event upsets (SEUs) and fault injection attacks, requiring the use of redundancy techniques such as fail-safe computing. Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. This work investigates circuit-level techniques and implements fail-safe computing processes as mitigation for SEUs and fault injection attacks on FPGAs. The analysis reveals vulnerabilities that exist in FPGAs over those in application-specific integrated circuits (ASIC); thus, requiring a more elaborate network of redundant circuits and checking logic. The reconfiguration capability of FPGAs adds complexity to fail-safe …

Periodic Information Leakage Fault Detection On A Risc-V Microprocessor, Idris Somoye

Electrical and Computer Engineering ETDs

The execution behavior of a Microprocessor (μP) in the presence of a fault is difficult to predict because of the complex interactions across pipeline stages and between functional units within the architecture. Fault effects are known to not introduce any type of anomaly in the input-output behavior for 10s of thousands to millions of clock cycles. These characteristics increase the difficulty of evaluating μP architectures for resilience to information leakage events, i.e., scenarios where a fault causes sensitive data such as an encryption key to be inadvertently diverted to a primary output channel. This dissertation explores two promising strategies for …

A Moving Target Architecture As A Side-Channel Countermeasure, Rachel M. Cazzola

Electrical and Computer Engineering ETDs

We investigate a novel side-channel attack countermeasure called Side-channel Power analysis Resistance for Encryption Algorithms using Dynamic partial reconfiguration (SPREAD). The countermeasure leverages a strategy that is best characterized as a moving target architecture. Modern field-programmable gate array (FPGA) architectures provide support for dynamic partial reconfiguration (DPR), a feature that allows real-time reconfiguration of portions of the programmable logic (PL) while the FPGA continues to carry out computing tasks. Using the Advanced Encryption Standard (AES), the proposed moving target architecture leverages DPR to change the implementation characteristics of the substitution boxes (SBOX) in real time. We present experimental hardware results …

Vi Energy-Efficient Memristor-Based Neuromorphic Computing Circuits And Systems For Radiation Detection Applications, Jorge Iván Canales Verdial

Electrical and Computer Engineering ETDs

Radionuclide spectroscopic sensor data is analyzed with minimal power consumption through the use of neuromorphic computing architectures. Memristor crossbars are harnessed as the computational substrate in this non-conventional computing platform and integrated with CMOS-based neurons to mimic the computational dynamics observed in the mammalian brain’s visual cortex. Functional prototypes using spiking sparse locally competitive approximations are presented. The architectures are evaluated for classification accuracy and energy efficiency. The proposed systems achieve a 90% true positive accuracy with a high-resolution detector and 86% with a low-resolution detector.

Evaluation Of The Dynamic Vision Sensor’S Photoreceptor Circuit For Infrared Event-Based Sensing, Zinah M. Alsaad

Electrical and Computer Engineering ETDs

For space surveillance applications, neuromorphic imaging is being studied as it may perform sensing and tracking tasks with less power and downstream datalink demand. The read-out of the event-based camera is made to only be sensitive to changes in the signals it receives from the photodetector, which results in a datastream of events indicating where and when changes in illumination occur. This is in contrast to the conventional framing camera, which produces images by essentially counting the electrons produced by light incident on each pixel’s photodetector. These cameras are commercially available with siliconbased detectors for applications involving visible wavelengths. However, …

Side Channel Attack Counter Measure Using A Moving Target Architecture, Jithin Joseph

Electrical and Computer Engineering ETDs

A novel countermeasure to side-channel power analysis attacks called Side-channel Power analysis Resistance for Encryption Algorithms using DPR or SPREAD is investigated in this thesis. The countermeasure leverages a strategy that is best characterized as a moving target architecture. Modern field programmable gate arrays (FPGA) architectures provide support for dynamic partial reconfiguration (DPR), a feature that allows real-time reconfiguration of the programmable logic (PL). The moving target architecture proposed in this work leverages DPR to implement a power analysis countermeasure to side-channel attacks, the most common of which are referred to as differential power analysis (DPA) and correlation power analysis …

Device-Level Predictive Modeling Of Extreme Electromagnetic Interference, Nishchay H. Sule

Electrical and Computer Engineering ETDs

Radio Frequency (RF) interference is a prominent issue for modern electronic devices. As device size and supply power shrink to meet the on-going demand for compact and complex Integrated Circuits (ICs), their susceptibility to external noise coupling to the input or power supply increases significantly. One such type of noise that acts upon a system to be considered is Extreme Electromagnetic Interference (EEMI). Previous works done to understand and evaluate the impact of EEMI onto a system or sub-system have been conducted on a statistical or empirical analysis level, which has led to complex and convoluted analysis, that requires significant …

Side-Channel Power Resistance For Encryption Algorithms Using Implementation Diversity, Ivan M. Bow

Electrical and Computer Engineering ETDs

This thesis paper investigates countermeasures to hardware side-channel attacks and proposes a new solution to this ever growing threat against data integrity and security. The side-channel attack methods, differential power analysis and correlation power analysis, are both very powerful techniques and are used to gain access to secrets inside of a field programmable gate array that are otherwise inaccessible, in particular the cryptographic key for the Advanced Encryption Standard algorithm. To counter these attacks, we propose a method of changing the internal hardware configuration of the field programmable gate array using dynamic partial reconfiguration. Using this method, we change the …

Algorithm For Computational Imaging On A Real-Time Hardware, Manish Bhattarai

Electrical and Computer Engineering ETDs

DRAMATIC advances in the field of computational and medical imaging over the past decades have enabled many critical applications such as night vision, medical diagnosis, quality control, and remote sensing. The increasing demand for image quality and its fidelity requires an increase in pixel count and a sophisticated post-processing mechanism to efficiently store, transmit, and analyze this massive data. There is an inherent trade-off between the generation of big data by such imaging systems and efficiency in extraction of useful information within real-time constraints, limiting the efficacy of such sensors in real-time decision-making systems. The traditional imaging system gets burdened …

The Effect Of Power Supply Ramp Time On Sram Puf's, Abdelrahman T. Elshafiey Mr.

Electrical and Computer Engineering ETDs

Physical unclonable functions (PUFs) are security primitives that exploit the device mismatches. PUFs are a promising solution for hardware cryptography and key storage. They are used in many security applications including identification, authentication and key generation. SRAM is one of the popular implementations of PUFs. SRAM PUFs offer the advantage, over other PUF constructions, of reusing resources (memories) that already exist in many designs.

In this thesis, for the first time, it is demonstrated that the start-up value of an SRAM PUF could be different depending on the SRAM power supply rising time. An analytical model has been developed to …