VLSI and Circuits, Embedded and Hardware Systems Commons^™

Dot Product Engine Based Neuromorphic Hardware For Continuous-Time Biomedical Signal Classification, Sanjeev Srinivasan

Master's Theses

Accurate diagnosis of pathological conditions from biomedical signals, such as electrocardiograms (ECGs) is often performed offline, making it time-consuming, costly, and inefficient, especially when abnormal patterns are rare and long-term monitoring generates large amounts of data. To address this, this work proposes a compact, scalable, and programmable neuromorphic system designed for real-time preliminary arrhythmia detection and classification using ECG signals, that can be extended to other biomedical signals. The proposed design processes ECG signals using a delta modulation-based spike encoder, followed by classification with a dot-product engine (DPE) based spiking neural network (SNN) processor and winner-take-all (WTA) circuit. The architecture …

Design Of An Extensible And Scalable Data Acquisition System For Pulse Shape Discrimination, Prince John

McKelvey School of Engineering Graduate Student Theses & Dissertations

This thesis presents the design and development of a highly scalable, end-to-end data acquisition (DAQ) system for nuclear physics experiments that can be deployed in configurations ranging from a few to thousands of detector channels. The system is built as an extensible platform composed of modular 16-channel chipboards that support a wide range of scintillator and detector types and perform real-time, on-board data sparsification and pulse-shape processing. Three versions of the chipboard have been fabricated to date.

The DAQ architecture is based on a family of analog pulse-shape-processing application- specific integrated circuits (ASICs) developed by the IC Design Laboratory at …

Reverse Engineering Bring Up And Profiling Of Multi-Fpga Systems, Henry A. Evans

Master's Theses

FPGAs have long been used for prototyping and verifying high-speed digital designs in industry and in academic research. As ASIC designs have grown in complexity and size, prototyping those designs on FPGAs has required multiple FPGAs that sometimes span multiple servers. Western Digital donated multiple FPGA-based systems to Cal Poly in 2023. These servers contain multiple high-end AMD FPGAs that are ideal for prototyping large high-speed digital designs, however the full documentation on how to use the servers and how the servers work was not provided. The servers did not come with any information on how to program the FPGAs, …

Open Source Asic Design Curriculum, Francisco Wilken

Master's Theses

The ever-growing importance of Application-Specific Integrated Circuits (ASICs) in a high-compute world necessitates that college graduates entering the workforce are well prepared to design them. This thesis details the design of novel ASIC curriculum, using open source tools to teach at the undergraduate level. By moving to a higher level of abstraction than classical transistor-focused coursework, chip design material can be made accessible earlier in an undergraduate degree. Additionally, open source tools provide a powerful, free, and portable platform for students to create their own designs, solving assignments focused on industry readiness. Finally, this thesis studies the results and challenges …

Bibliometric Review Of Fpga Based Implementation Of Cnn, Priti Shahane, Piyush Tyagi, Purba Saha, Shravan Sainath, Swanand Bedekar

Library Philosophy and Practice (e-journal)

Nowadays Convolution Neural Network (CNN) has become the state of the art for machine learning algorithms due to their high accuracy. However, implementation of CNN algorithms on hardware platforms becomes challenging due to high computation complexity, memory bandwidth and power consumption. Hardware accelerators such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC) are suitable platforms to model CNN algorithms. Recently FPGAs have been considered as an attractive platform for CNN implementation. Modern FPGAs have various embedded hardware and software blocks such as a soft processor, DSP slice and memory blocks. These embedded resources …

Fault Modeling And Test Vector Generation For Asic Devices Exposed To Space Single Event Environment, Ahmed Mohamed

Theses and Dissertations

This work aims at providing a concise automated flow to predict the effect of Single Event Transients (SETs) on ASIC chips by developing a method to characterize the circuit susceptibility to SET pulses propagation and then generation of the required input vectors that sensitize the victim paths. A new enhanced method for SET electrical propagation modeling is proposed and compared to a previously published analytical model. The method was applied on different standard cells libraries built over XFAB Xh018 technology and verified for accuracy against simulations. The new method showed enhancement in accuracy compared with previous work in literature. Industrial …

Cmos Radioactive Isotope Identification With Multichannel Analyzer And Embedded Neural Network, Samuel Murray

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

A radiation detection and identification system is designed and implemented to perform gamma ray spectroscopy on radioactive sources and identify which isotopes are present in the sources. A multichannel analyzer is implemented on an ASIC to process the signal produced from gamma rays detected by a scintillator and photomultiplier tube and to quantize the gamma ray energies to build a histogram. A fast, low memory embedded neural network is implemented on a microcontroller ASIC to identify the isotopes present in the gamma ray histogram produced by the multichannel analyzer in real time.

Advisors: Sina Balkir and Michael W. Hoffman

Cmos Smart Camera With Focal Plane Neighborhood-Parallel Image Processing, Joseph A. Schmitz

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

A neighbhorhood-based smart camera architecture is designed and implemented in a 0.13 μm CMOS technology. Each 8 × 8 region of pixels contains a small processor with local memory, which are tiled to form a full-resolution camera. Each processor operates in parallel, enabling high-speed image processing suitable for tracking and recognition tasks. The architecture features the programming flexibility of designs us- ing chip-level and row-level processors while preserving the scalability of pixel-parallel processing elements. The neighborhood processors are implemented physically be- tween the pixel photodiodes, creating multiple design challenges that are discussed in detail.

Advisors: Sina Balkir and Michael W. …

Cad Tools For Synthesis Of Sleep Convention Logic, Parviz Palangpour

Graduate Theses and Dissertations

This dissertation proposes an automated flow for the Sleep Convention Logic (SCL) asynchronous design style. The proposed flow synthesizes synchronous RTL into an SCL netlist. The flow utilizes commercial design tools, while supplementing missing functionality using custom tools. A method for determining the performance bottleneck in an SCL design is proposed. A constraint-driven method to increase the performance of linear SCL pipelines is proposed. Several enhancements to SCL are proposed, including techniques to reduce the number of registers and total sleep capacitance in an SCL design.

Silicon Germanium Sram And Rom Designs For Wide Temperature Range Space Applications, Matthew Barlow

Graduate Theses and Dissertations

This thesis presents a design flow from specifications and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1 kilobyte that are suitable for lunar environments. The design uses the IBM SiGe 5AM BiCMOS 0.5 micron process for a synchronous memory system capable of operating at a clock frequency of 25 MHz. Radiation mitigation techniques are discussed and implemented to harden the design against total ionizing dose (TID), single-event upset (SEU), and single-event latch-up (SEL). The memory arrays are also designed to operate over the wide temperature range of -180 °C to 125 °C. Design, …

Full Custom Vlsi Design Of On-Line Stability Checkers, Chris Y. Lee

Master's Theses

A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.

A method for concurrent fault testing called On-line Stability Checking …