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Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems
Logical Modeling Of Adiabatic Logic Circuits Using Vhdl, Lee Belfore
Logical Modeling Of Adiabatic Logic Circuits Using Vhdl, Lee Belfore
Electrical & Computer Engineering Faculty Publications
The underlying nature of adiabatic circuits is most accurately characterized at the circuit level as it is for traditional technologies. In order to scale system designs for adiabatic logic technologies, modeling of adiabatic circuits at the logic level is necessary. Logic level models of adiabatic logic circuits can facilitate the design, development, and verification of large scale digital systems that may be infeasible using circuit simulators. Adiabatic logic circuits can be powered with a four stage power clock consisting of idle, charge, hold, and recover stages that provides for adiabatic charging and charge recovery to give adiabatic circuits their low …
Asynchronous Circuit Synthesis Using Multi-Threshold Null Convention Logic, Nicholas Renoudet Mize
Asynchronous Circuit Synthesis Using Multi-Threshold Null Convention Logic, Nicholas Renoudet Mize
Graduate Theses and Dissertations
As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away with the constrains of a clock, asynchronous sequential circuit designs can achieve a much greater level of efficiency. The utilization of asynchronous logic synthesis flows has enabled researchers to better implement asynchronous circuit designs which have been optimized using the same industry standard tools that are already used in sequential synchronous designs. This thesis offers a new flow for such tools which implements the MTNCL asynchronous circuit architecture.
Differential Power Analysis In-Practice For Hardware Implementations Of The Keccak Sponge Function, Nathaniel Graff
Differential Power Analysis In-Practice For Hardware Implementations Of The Keccak Sponge Function, Nathaniel Graff
Master's Theses
The Keccak Sponge Function is the winner of the National Institute of Standards and Technology (NIST) competition to develop the Secure Hash Algorithm-3 Standard (SHA-3). Prior work has developed reference implementations of the algorithm and described the structures necessary to harden the algorithm against power analysis attacks which can weaken the cryptographic properties of the hash algorithm. This work demonstrates the architectural changes to the reference implementation necessary to achieve the theoretical side channel-resistant structures, compare their efficiency and performance characteristics after synthesis and place-and-route when implementing them on Field Programmable Gate Arrays (FPGAs), publish the resulting implementations under the …
Conversion Of Digital Circuits Labs, Caleb N. Taber
Conversion Of Digital Circuits Labs, Caleb N. Taber
Undergraduate Honors Theses
The engineering technology department at ETSU currently lacks a modern method to teach digital circuits. The aim of this thesis is to convert our current digital circuits labs to equivalent labs suited to run on the Basys 3. The Basys has several advantages over the aging NI Elvis boards (and now just breadboards) currently in use. The first advantage is that the Basys gives students a taste of FPGA programming without being overwhelmingly; like the systems currently in place for the digital signal processing class. The Basys is also a more modern system; our current integrated circuit and breadboard system …
Synthesizing Optimal Fixed-Point Arithmetic For Embedded Signal Processing, Kenneth J. Hass
Synthesizing Optimal Fixed-Point Arithmetic For Embedded Signal Processing, Kenneth J. Hass
Faculty Conference Papers and Presentations
No abstract provided.