VLSI and Circuits, Embedded and Hardware Systems Commons^™

Asynchronous Circuit Synthesis Using Multi-Threshold Null Convention Logic, Nicholas Renoudet Mize

Graduate Theses and Dissertations

As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away with the constrains of a clock, asynchronous sequential circuit designs can achieve a much greater level of efficiency. The utilization of asynchronous logic synthesis flows has enabled researchers to better implement asynchronous circuit designs which have been optimized using the same industry standard tools that are already used in sequential synchronous designs. This thesis offers a new flow for such tools which implements the MTNCL asynchronous circuit architecture.

Efficacy Of Multi-Threshold Null Convention Logic In Low-Power Applications, Brent Bell

Graduate Theses and Dissertations

In order for an asynchronous design paradigm such as Multi-Threshold NULL Convention Logic (MTNCL) to be adopted by industry, it is important for circuit designers to be aware of its advantages and drawbacks especially with respect to power usage. The power tradeoff between MTNCL and synchronous designs depends on many different factors including design type, circuit size, process node, and pipeline granularity. Each of these design dimensions influences the active power and the leakage power comparisons. This dissertation analyzes the effects of different design dimensions on power consumption and the associated rational for these effects. Results show that while MTNCL …

Music Synthesizer Senior Project: Danalog, Vikrant A. Marathe

Electrical Engineering

The Danalog is a 25 key portable digital music synthesizer that uses multiple synthesis methods and effects to generate sounds. Sound varieties included three synthesis methods including FM, subtractive, and sample-based, with up to eight adjustable parameters, at least four effects, including reverb, chorus, and flange, with five adjustable parameters, and at least two note polyphony, and a five band equalizer. The user would be able to adjust these effects using digital encoders and potentiometers and view the settings on two LCD screens. The finals project was unable to meet the original design requirements. The FM synthesis method was primarily …

Danalog: Digital Music Synthesizer, Evan R. Lew

Electrical Engineering

The Danalog is a 25 key portable digital music synthesizer that uses multiple synthesis methods and effects to generate sounds. Sound varieties included three synthesis methods including FM, subtractive, and sample-based, with up to eight adjustable parameters, at least four effects, including reverb, chorus, and flange, with five adjustable parameters, and at least two note polyphony, and a five band equalizer. The user would be able to adjust these effects using digital encoders and potentiometers and view the settings on two LCD screens.

The finals project was unable to meet the original design requirements. The FM synthesis method was primarily …

Music Synthesizer Senior Project: Individual Report, Bryan Bellin

Electrical Engineering

No abstract provided.

El Capitán: Cal Poly Rose Float Digital Drive System, Gregory Raffi Baghdikian

Computer Engineering

In today’s world of smartphones, self-driving cars, and internet-connected coffee makers, it seems as if computers are contained in everything around us. These “embedded systems” have become critical components of our lives, improving everything about the things they control, from cost, to speed, to simplicity. One area that embedded systems has hardly gained a foothold is in the world of floatbuilding. Most of the floats in the Tournament of Roses Parade, including the one built jointly by Cal Poly San Luis Obispo and Cal Poly Pomona, are technologically very simple, using mostly analog components and rudimentary discrete digital logic to …

High Temperature Cmos Silicon Carbide Asynchronous Circuit Design, Landon John Caley

Graduate Theses and Dissertations

Designing a digital circuit to operate in an extreme temperature range is a challenge with increasing demand for a solution. Large variations in temperature have a distinct impact on electron mobilities causing substantial changes to the threshold voltage of the devices. These physical changes affect the setup and hold times of clocked components, such as D-Flip Flops, of a traditional synchronous digital circuit. Focusing primarily on high temperature circuit operation, this dissertation presents a digital circuit design methodology pairing an asynchronous circuit design paradigm called NULL Convention Logic (NCL) as well as traditional Boolean circuitry with a wide-bandgap semiconductor material, …

Design And Analysis Of An Adaptive Asynchronous System Architecture For Energy Efficiency, Brent Michael Hollosi

Graduate Theses and Dissertations

Power has become a critical design parameter for digital CMOS integrated circuits. With performance still garnering much concern, a central idea has emerged: minimizing power consumption while maintaining performance. The use of dynamic voltage scaling (DVS) with parallelism has shown to be an effective way of saving power while maintaining performance. However, the potency of DVS and parallelism in traditional, clocked synchronous systems is limited because of the strict timing requirements such systems must comply with. Delay-insensitive (DI) asynchronous systems have the potential to benefit more from these techniques due to their flexible timing requirements and high modularity. This dissertation …

Discrete Alarm Clock, Travis Moore, Collin Barth

Electrical Engineering

The standard alarm clock, as used daily by millions worldwide, has clear room for modification and improvement.  This paper documents an implementation that rectifies many of these flaws.  Improvements include adjustable snooze length, an IR remote for ease of use, and an RF headset for discrete alarm use or potential incorporation into a device much like a hearing aid.  The processes involved in creating a digital alarm clock, as well as the obstacles met in the implementation of the enhanced design, are detailed within.