Open Access. Powered by Scholars. Published by Universities.®
VLSI and Circuits, Embedded and Hardware Systems Commons™
Open Access. Powered by Scholars. Published by Universities.®
- Discipline
- Keyword
- Publication
- Publication Type
Articles 1 - 3 of 3
Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems
Max Operation In Statistical Static Timing Analysis On The Non-Gaussian Variation Sources For Vlsi Circuits, Abu M. Baker
Max Operation In Statistical Static Timing Analysis On The Non-Gaussian Variation Sources For Vlsi Circuits, Abu M. Baker
UNLV Theses, Dissertations, Professional Papers, and Capstones
As CMOS technology continues to scale down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. If this uncertainty is not properly handled, it may become the bottleneck of CMOS technology improvement. As a result, deterministic analysis is no longer conservative and may result in either overestimation or underestimation of the circuit delay. As we know that Static-Timing Analysis (STA) is a deterministic way of computing the delay imposed by the circuits design and layout. It is based on a predetermined set of possible events of process variations, also called corners of …
Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker
Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker
College of Engineering: Graduate Celebration Programs
As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. Although Static-Timing Analysis (STA) remains an excellent tool, current trends in process scaling have imposed significant difficulties to STA. As one of the promising solutions, Statistical static timing analysis (SSTA) has become the frontier research topic in recent years in combating such variation effects. This poster will be focusing on two aspects of SSTA and its applications in VLSI designs: (1) Statistical timing modeling and analysis; and (2) Architectural implementations of the atomic operations (max and add) using …
Parameterizable Network-On-Chip Emulation Framework, Jaya Suseela
Parameterizable Network-On-Chip Emulation Framework, Jaya Suseela
UNLV Theses, Dissertations, Professional Papers, and Capstones
Networks-on-Chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. But there is no public accessible HDL synthesizable NoC framework which connects industrial level cores and runs real applications on them. Moreover, many challenging research problems remain unsolved at all levels of design abstraction; design exploration of NoC architecture for applications, scheduling and mapping algorithms, evaluation of switching, topology or routing algorithm for efficient execution of application and optimizing communication cost, area, energy etc Solution to solve the above problem calls for the development of synthesizable, parameterizable NoC Framework that would evaluate and implement the above …