VLSI and Circuits, Embedded and Hardware Systems Commons^™

Dot Product Engine Based Neuromorphic Hardware For Continuous-Time Biomedical Signal Classification, Sanjeev Srinivasan

Master's Theses

Accurate diagnosis of pathological conditions from biomedical signals, such as electrocardiograms (ECGs) is often performed offline, making it time-consuming, costly, and inefficient, especially when abnormal patterns are rare and long-term monitoring generates large amounts of data. To address this, this work proposes a compact, scalable, and programmable neuromorphic system designed for real-time preliminary arrhythmia detection and classification using ECG signals, that can be extended to other biomedical signals. The proposed design processes ECG signals using a delta modulation-based spike encoder, followed by classification with a dot-product engine (DPE) based spiking neural network (SNN) processor and winner-take-all (WTA) circuit. The architecture …

Design And Verification Of The Multi-Slit Solar Explorer Camera Field Programmable Gate Arrays, Jordan M. Johnson

All Graduate Reports and Creative Projects, Fall 2023 to Present

The Multi-Slit Solar Explorer, or MUSE, is a NASA mission that will take images of the Sun to study solar flares and the solar corona. The mission will provide insight into the mechanisms behind space weather. The mission consists of two cameras: the Spectrograph (SG), and the Context Imager (CI). The Utah State University Space Dynamics Laboratory is providing both cameras for the mission.

This report describes a part of the design and verification process for a central component on these cameras known as the Field Programmable Gate Arrays (FPGAs). These FPGAs are programmed to acquire, handle, and send images …

Design Of An Extensible And Scalable Data Acquisition System For Pulse Shape Discrimination, Prince John

McKelvey School of Engineering Graduate Student Theses & Dissertations

This thesis presents the design and development of a highly scalable, end-to-end data acquisition (DAQ) system for nuclear physics experiments that can be deployed in configurations ranging from a few to thousands of detector channels. The system is built as an extensible platform composed of modular 16-channel chipboards that support a wide range of scintillator and detector types and perform real-time, on-board data sparsification and pulse-shape processing. Three versions of the chipboard have been fabricated to date.

The DAQ architecture is based on a family of analog pulse-shape-processing application- specific integrated circuits (ASICs) developed by the IC Design Laboratory at …

Reverse Engineering Bring Up And Profiling Of Multi-Fpga Systems, Henry A. Evans

Master's Theses

FPGAs have long been used for prototyping and verifying high-speed digital designs in industry and in academic research. As ASIC designs have grown in complexity and size, prototyping those designs on FPGAs has required multiple FPGAs that sometimes span multiple servers. Western Digital donated multiple FPGA-based systems to Cal Poly in 2023. These servers contain multiple high-end AMD FPGAs that are ideal for prototyping large high-speed digital designs, however the full documentation on how to use the servers and how the servers work was not provided. The servers did not come with any information on how to program the FPGAs, …

Periodic Information Leakage Fault Detection On A Risc-V Microprocessor, Idris Somoye

Electrical and Computer Engineering ETDs

The execution behavior of a Microprocessor (μP) in the presence of a fault is difficult to predict because of the complex interactions across pipeline stages and between functional units within the architecture. Fault effects are known to not introduce any type of anomaly in the input-output behavior for 10s of thousands to millions of clock cycles. These characteristics increase the difficulty of evaluating μP architectures for resilience to information leakage events, i.e., scenarios where a fault causes sensitive data such as an encryption key to be inadvertently diverted to a primary output channel. This dissertation explores two promising strategies for …

Analyzing A Software Based Lossy Compression Algorithm On An Fpga Platform, Tripp Herlong

All Theses

In HPC, the ability to generate data is outpacing our hardware capabilities of storing said data. This presents the need for compression so we can keep important data preserved without costly hardware upgrades or worrying about hardware speed limitations. Traditional forms of compression are software based, which presents a speed issue that can lead to bottlenecks when storing data.Scientific data lossy compression methods such as SZ enable a speedup on memory transfer by simplifying computation to minimize the essential data size. SZx is a lightweight version of the popular SZ floating point compressor that may benefit from hardware acceleration. This …

A Sindy Hardware Accelerator For Efficient System Identification On Edge Devices, Michael Sean Gallagher

Master's Theses

The SINDy (Sparse Identification of Non-linear Dynamics) algorithm is a method of turning a set of data representing non-linear dynamics into a much smaller set of equations comprised of non-linear functions summed together. This provides a human readable system model the represents the dynamic system analyzed. The SINDy algorithm is important for a variety of applications, including high precision industrial and robotic applications. A Hardware Accelerator was designed to decrease the time spent doing calculations. This thesis proposes an efficient hardware accelerator approach for a broad range of applications that use SINDy and similar system identification algorithms. The accelerator is …

A Novel Processor Architecture Implementing The Stacked Error Diffusion Algorithm And Its Zynq-Based Realization, Qishi Hu

Theses and Dissertations--Electrical and Computer Engineering

Digital halftoning reproduces continuous-tone images using patterns of black and white dots, while multitoning extends this concept by incorporating inks with intermediate intensities. These techniques are extensively utilized in the printing industry to accommodate the limited range of inks available in printers. Stacked error diffusion is a high-quality multitoning algorithm that adheres to the blue-noise dithering standard. This thesis research studies the potential parallelism inherent in the algorithm and introduces the design of a novel processor architecture optimized for efficient execution. The architecture is realized on an FPGA development board featuring a Zynq SoC. Additionally, the hardware prototype can also …

Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya

Theses and Dissertations

High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a …

Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad

Theses and Dissertations

Running computer vision algorithms requires complex devices with lots of computing power, these types of devices are not well suited for space deployment. The harsh radiation environment and limited power budgets have hindered the ability of running advanced computer vision algorithms in space. This problem makes running an on-orbit servicing detection algorithm very difficult. This work proposes using a low powered FPGA to accelerate the computer vision algorithms that enable satellite component feature extraction. This work uses AMD/Xilinx’s Zynq SoC and DPU IP to run model inference. Experiments in this work centered around improving model post processing by creating implementations …

Neural Compression Inference Accelerator: A Cost And Energy-Effective Alternative To Conventional Machine Learning Inference Methods, Matthew Wallace

Master's Theses

Recent developments in machine learning and artificial intelligence have sparked an influx of workloads that require specialized computer hardware for cloud services. The hardware running machine learning models predominantly consists of graphics processing units (GPUs) and tensor processing units (TPUs). However, these com- ponents are expensive for cloud services to purchase, costly for customers to rent, prone to price spikes, and energy-intensive. In this research we show that both cloud services and customers would benefit from utilizing field programmable gate arrays (FPGAs) to alleviate the aforementioned challenges. An FPGA can be configured as a machine learning accelerator, operating similarly to …

Bibliometric Review Of Fpga Based Implementation Of Cnn, Priti Shahane, Piyush Tyagi, Purba Saha, Shravan Sainath, Swanand Bedekar

Library Philosophy and Practice (e-journal)

Nowadays Convolution Neural Network (CNN) has become the state of the art for machine learning algorithms due to their high accuracy. However, implementation of CNN algorithms on hardware platforms becomes challenging due to high computation complexity, memory bandwidth and power consumption. Hardware accelerators such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC) are suitable platforms to model CNN algorithms. Recently FPGAs have been considered as an attractive platform for CNN implementation. Modern FPGAs have various embedded hardware and software blocks such as a soft processor, DSP slice and memory blocks. These embedded resources …

Side Channel Attack Counter Measure Using A Moving Target Architecture, Jithin Joseph

Electrical and Computer Engineering ETDs

A novel countermeasure to side-channel power analysis attacks called Side-channel Power analysis Resistance for Encryption Algorithms using DPR or SPREAD is investigated in this thesis. The countermeasure leverages a strategy that is best characterized as a moving target architecture. Modern field programmable gate arrays (FPGA) architectures provide support for dynamic partial reconfiguration (DPR), a feature that allows real-time reconfiguration of the programmable logic (PL). The moving target architecture proposed in this work leverages DPR to implement a power analysis countermeasure to side-channel attacks, the most common of which are referred to as differential power analysis (DPA) and correlation power analysis …

Data Processing Electronics For An Ultra-Fast Single-Photon Counting Camera, Jackson Hyde

McKelvey School of Engineering Graduate Student Theses & Dissertations

Localizing photon arrivals with high spatial (megapixel) and temporal (sub-nanosecond) resolution would be transformative for a number of applications, including single-molecule super-resolution fluorescence microscopy. Here, the Data Processing Field Programmable Gate Array (FPGA) is developed as an ultra-fast computational platform built on an FPGA for a microchannel plate (MCP)-photomultiplier tube (PMT) based single-photon counting camera. Each photon is converted by the MCP-PMT into an electron cloud that generates current pulses across a 50×50 cross-strip anode. The Data Processing FPGA executes a massively parallel center-of-gravity coordinate determination algorithm on the digitized current pulses to determine a 2D position and time of …

An Investigation Into Partitioning Algorithms For Automatic Heterogeneous Compilers, Antonio M. Leija

Master's Theses

Automatic Heterogeneous Compilers allows blended hardware-software solutions to be explored without the cost of a full-fledged design team, but limited research exists on current partitioning algorithms responsible for separating hardware and software. The purpose of this thesis is to implement various partitioning algorithms onto the same automatic heterogeneous compiler platform to create an apples to apples comparison for AHC partitioning algorithms. Both estimated outcomes and actual outcomes for the solutions generated are studied and scored. The platform used to implement the algorithms is Cal Poly’s own Twill compiler, created by Doug Gallatin last year. Twill’s original partitioning algorithm is chosen …

Fpga To Power System Theorization For A Fault Location And Specification Algorithm, Christina Yeoman

Theses and Dissertations--Electrical and Computer Engineering

Fault detection and location algorithms have allowed for the power industry to alter the power grid from the traditional model to becoming a smart grid. This thesis implements an already established algorithm for detecting faults, as well as an impedance-based algorithm for detecting where on the line the fault has occurred and develops a smart algorithm for future HDL conversion using Simulink. Using the algorithms, the ways in which this implementation can be used to create a smarter grid are the fundamental basis for this research. Simulink was used to create a two-bus power system, create environment variables, and then …