VLSI and Circuits, Embedded and Hardware Systems Commons^™

Versatile Potentiostat With Optional Computer Control, Gary L. Fuller, William A. Russell Jr., Roger M. Hawk, James D. Wilson, P. D. Bratton

Journal of the Arkansas Academy of Science

A versatile potentiostat which can supply a maximum of 125 ma is described. The potentiostat uses readily available electronic components and an interface is detailed which allows the potentiostat optional computer control.

Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson

Computer Science: Faculty Publications and Other Works

Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda + lg n lg lg n) with probability 1-O(1/n). The best previous …

Lower Bounds On The Area Of Finite-State Machines, M. J. Foster, Ronald I. Greenberg

Computer Science: Faculty Publications and Other Works

There are certain straightforward algorithms for laying out finite-state machines. This paper shows that these algorithm are optimal in the worst case for machines with fixed alphabets. That is, for any s and k, there is a deterministic finite-state machine with s states and k symbols such that any layout algorithm requires Ω(ks log s) area to lay out its realization. Similarly, any layout algorithm requires Ω(ks^2) area in the worst case for nondeterministic finite-state machines with s states and k symbols.

Mulch: A Multi-Layer Channel Router Using One, Two, And Three Layer Partitions, Ronald I. Greenberg, Alex T. Ishii, Alberto L. Sangiovanni-Vincentelli

Computer Science: Faculty Publications and Other Works

Chameleon, a channel router for three layers of interconnect, has been implemented to accept specification of an arbitrary number of layers. Chameleon is based on a strategy of decomposing the multilayer problem into two- and three-layer problems in which one of the layers is reserved primarily for vertical wire runs and the other layer(s) for horizontal runs. In some situations, however, it is advantageous to consider also layers that allow the routing of entire nets, using both horizontal and vertical wires. MulCh is a multilayer channel router that extends the algorithms of Chameleon in this direction. MulCh can route channels …

Surface-To-Surface Transition Via Electromagnetic Coupling Of Coplanar Waveguides, Robert W. Jackson, David W. Matolak

Faculty Publications

A transition is investigated which couples coplanar waveguide on one substrate surface (a motherboard) to coplanar waveguide on another substrate surface (a semiconductor chip or subarray) placed above the first. No wire bonds are necessary. A full-wave analysis using coupled line theory is presented and verified experimentally. The use of this transition for coupling to millimeter-wave integrated circuits is discussed.

Randomized Routing On Fat-Trees, Ronald I. Greenberg

Computer Science: Faculty Publications and Other Works

Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda+lgnlglgn) with probability 1-O(1/ …

High Performance Switching Circuits For Vlsi, Ali Reza Feizi

Electrical & Computer Engineering Theses & Dissertations

Interconnection topology and device performance are of major concern in the design of LSI/VLSI systems, Pass networks are very suitable in this regard because of low power consumption, high density, and simple interconnection topology. A special type of pass networks called Binary Tree Structured (BTS) pass networks uses almost minimum number of transistors for the design of switching circuits. An algorithmic procedure is developed here for BTS pass networks which is very efficient in terms of both execution time and memory space. Based on these networks, the necessary and sufficient conditions are derived for the design of multiple-output pass networks. …

Circuit Analysis Of A Gas Flow Switch, Teri Marie Owens

Electrical & Computer Engineering Theses & Dissertations

The circuit analysis of a gas flow switch is presented. The objective of the analysis is to model the switching process during spark gap breakdown. This information is useful in understanding switch operation and identifying ways to improve switch performance.

A lumped circuit model is used to describe a gas flow switch during the switching process. Certain circuit element values are determined experimentally through static tests. Other component values, including a time-varying switch resistance and inductance, are estimated from current measurements. In particular, unknown constants in expressions for gap resistance and inductance are determined using an iterative parameter estimation technique. …