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VLSI and Circuits, Embedded and Hardware Systems Commons™
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- Integrated circuits--Very large scale integration (9)
- VHDL (Computer hardware description language) (3)
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Articles 1 - 26 of 26
Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems
Implementation And Performance Of Factorized Backprojection On Low-Cost Commercial-Off-The-Shelf Hardware, Alec C. Rasmussen
Implementation And Performance Of Factorized Backprojection On Low-Cost Commercial-Off-The-Shelf Hardware, Alec C. Rasmussen
Theses and Dissertations
Traditional Synthetic Aperture Radar (SAR) systems are large, complex, and expensive platforms that require significant resources to operate. The size and cost of the platforms limits the potential uses of SAR to strategic level intelligence gathering or large budget research efforts. The purpose of this thesis is to implement the factorized backprojection SAR image processing algorithm in the C++ programming language and test the code's performance on a low cost, low size, weight, and power (SWAP) computer: a Raspberry Pi Model B. For a comparison of performance, a baseline implementation of filtered backprojection is adapted to C++ from pre-existing MATLAB® …
An Openeaagles Framework Extension For Hardware-In-The-Loop Swarm Simulation, Derek B. Worth
An Openeaagles Framework Extension For Hardware-In-The-Loop Swarm Simulation, Derek B. Worth
Theses and Dissertations
Unmanned Aerial Vehicle (UAV) swarm applications, algorithms, and control strategies have experienced steady growth and development over the past 15 years. Yet, to this day, most swarm development efforts have gone untested and thus unimplemented. Cost of aircraft systems, government imposed airspace restrictions, and the lack of adequate modeling and simulation tools are some of the major inhibitors to successful swarm implementation. This thesis examines how the OpenEaagles simulation framework can be extended to bridge this gap. This research aims to utilize Hardware-in-the-Loop (HIL) simulation to provide developers a functional capability to develop and test the behaviors of scalable and …
Intrinsic Physical Layer Authentication Of Integrated Circuits, William E. Cobb, Michael A. Temple, Rusty O. Baldwin, Eric W. Garcia, Eric D. Lapse
Intrinsic Physical Layer Authentication Of Integrated Circuits, William E. Cobb, Michael A. Temple, Rusty O. Baldwin, Eric W. Garcia, Eric D. Lapse
AFIT Patents
A system and method of generating and comparing a fingerprint for an integrated circuit is provided. A sensor module captures electromagnetic emissions from the integrated circuit. A feature extraction module extracts discriminating features from the captured electromagnetic emissions. A classifier training module generates a plurality of authentication fingerprints of the integrated circuit from the extracted discriminating features creating a reference fingerprint template for the integrated circuit. The reference template for the integrated circuit is stored in a database. For authentication, the reference fingerprint template from the database is compared to the generated authentication fingerprint.
Digital Display With Integrated Computing Circuit, Ronald S. Cok, John W. Harmer, Michael E. Miller
Digital Display With Integrated Computing Circuit, Ronald S. Cok, John W. Harmer, Michael E. Miller
AFIT Patents
A digital display device includes a display substrate; an array of pixels formed on the display substrate; an array of driving circuits located on the display substrate, each driving circuit electrically connected to one or more pixels for controlling a pixel current provided to each pixel; an array of computing circuits located on the display substrate, each computing circuit including circuits for signal or image processing and for communicating with neighboring computing circuits; a plurality of electrical conductors formed on the display substrate and connected to each of the driving circuits and digital computing circuits, wherein each computing circuit is …
Dynamic Polymorphic Reconfiguration To Effectively “Cloak” A Circuit’S Function, Jeffrey L. Falkinburg
Dynamic Polymorphic Reconfiguration To Effectively “Cloak” A Circuit’S Function, Jeffrey L. Falkinburg
Theses and Dissertations
Today's society has become more dependent on the integrity and protection of digital information used in daily transactions resulting in an ever increasing need for information security. Additionally, the need for faster and more secure cryptographic algorithms to provide this information security has become paramount. Hardware implementations of cryptographic algorithms provide the necessary increase in throughput, but at a cost of leaking critical information. Side Channel Analysis (SCA) attacks allow an attacker to exploit the regular and predictable power signatures leaked by cryptographic functions used in algorithms such as RSA. In this research the focus on a means to counteract …
Evaluation Of The Single Keybit Template Attack, Eric W. Garcia
Evaluation Of The Single Keybit Template Attack, Eric W. Garcia
Theses and Dissertations
Side Channel leakage is a serious threat to secure devices. Cryptographic information extraction is possible after examining any one of the various side channels, including electromagnetic. This work contributes a new method to achieve such a purpose. The Single Keybit Template Attack (SKTA) is introduced as a means to extract encryption keys from embedded processors and other integrated circuit devices performing DES encryptions by passively monitoring and exploiting unintentional RF emissions. Key extraction is accomplished by creating two templates for each bit value of the key based on instantaneous amplitude responses as a device executes DES operations. The resultant templates …
Removing Redundant Logic Pathways In Polymorphic Circuits, Hanseok Kim
Removing Redundant Logic Pathways In Polymorphic Circuits, Hanseok Kim
Theses and Dissertations
Evaluating the quality of software and circuit obfuscators is a research goal of great interest. However, there exists little research about evaluation of obfuscation effectiveness through analyzing and investigating redundancies found in the obfuscated variants. In this research, we consider programs represented as structural combinational circuits and then analyze obfuscated variants of those circuits through a tool that produces functionally equivalent variants based on subcircuit selection and replacement. We then consider how Boolean logic and reduction affects the size and levelization of circuit variants, giving us a concrete metric by which to consider obfuscation effectiveness. To accomplish these goals, we …
A Modular Mixed Signal Vlsi Design Approach For Digital Radar Applications, Brian M. Brakus
A Modular Mixed Signal Vlsi Design Approach For Digital Radar Applications, Brian M. Brakus
Theses and Dissertations
This study explores the idea of building a library of VHDL configurable components for use in digital radar applications. Configurable components allows a designer to choose which components he or she needs and configures those components for a specific application. By doing this, design time for ASICs and FPGAs is shortened because the components are already designed and tested. This idea is demonstrated with a configurable dynamic pipelinable fast fourier transform. Many FFT implementations exist, but this implementation is both configurable and dynamic. Pre-synthesis customization allows the FFT to be tailored to almost any DSP application, and the dynamic property …
Microdot - A Four-Bit Microcontroller Designed For Distributed Low-End Computing In Satellites, Anthony R. Woodcock
Microdot - A Four-Bit Microcontroller Designed For Distributed Low-End Computing In Satellites, Anthony R. Woodcock
Theses and Dissertations
Many satellites are an integrated collection of sensors and actuators that require dedicated real-time control. For single processor systems, additional sensors require an increase in computing power and speed to provide the multi-tasking capability needed to service each sensor. Faster processors cost more and consume more power, which taxes a satellite's power resources and may lead to shorter satellite lifetimes. An alternative design approach is a distributed network of small and low power microcontrollers designed for space that handle the computing requirements of each individual sensor and actuator. The design of microdot, a four-bit microcontroller for distributed low-end computing, is …
Microdot-A 4-Bit Synchronous Microcontroller For Space Applications, Kirby M. Watson
Microdot-A 4-Bit Synchronous Microcontroller For Space Applications, Kirby M. Watson
Theses and Dissertations
Satellites have limited power budgets due to the amount of power collected by the satellite's solar panels. The goal is to have a wide range of functionality, while running off a limited power source. Large microprocessors use large amounts of power to report back temperature and chemical sensor data to ground stations. By using small micro controllers to perform the data collection and minimizing the usage of the larger microprocessors, the satellites will save power. A prototype design of the Microdot 4-bit micro controller for space applications is presented. Requirements for the Microdot, such as microwatt power consumption and 23 …
Approximation And Optimization Of An Auditory Model For Realization In Vlsi Hardware, Samuel L. Sangregory
Approximation And Optimization Of An Auditory Model For Realization In Vlsi Hardware, Samuel L. Sangregory
Theses and Dissertations
The Auditory Image Model (AIM) is a software tool set developed to functionally model the role of the ear in the human hearing process. AIM includes detailed filter equations for the major functional portions of the ear. Currently, AIM is run on a workstation and requires 10 to 100 times real-time to process audio information and produce an auditory image. An all-digital approximation of the AIM which is suitable for implementation in very large scale integrated circuits is presented. This document details the mathematical models of AIM and the approximations and optimizations used to simplify the filtering and signal processing …
Accelerating Conservative Parallel Simulation Of Vhdl Circuits, Joel F. Hurford
Accelerating Conservative Parallel Simulation Of Vhdl Circuits, Joel F. Hurford
Theses and Dissertations
This research effort considers heuristic and cost model based techniques for the optimal partitioning of VHDL circuits for parallel simulation. Correlation statistics are gathered on a wide variety of graph-based a priori parameters. Linear regression is used to identify significant parameters for inclusion in a representative cost model. Driving a greedy search, this cost model is used to improve upon initial heuristic partitions. The influence of feedback dominated previous research so a no-feedback algorithm is used to create the initial partition The circuits studied range from 1,050 to 4,243 gates.
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Theses and Dissertations
Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural …
A Physics-Based Heterojunction Bipolar Transistor Model For Integrated Circuit Simulation, James A. Fellows
A Physics-Based Heterojunction Bipolar Transistor Model For Integrated Circuit Simulation, James A. Fellows
Theses and Dissertations
The purpose of this research effort was to derive a physics-based dc model for a Heterojunction Bipolar Transistor HBT. The dc model was then linearized to arrive at a small-signal model that accurately predicts the devices electrical behavior at microwave frequencies. This new model offers features not found in previous analytical or physics-based HBT models such as consideration of a cylindrical emitter-base geometry and is direct implementation into SPICE Simulation Program with Integrated Circuit Emphasis. The device model parameters were determined from a knowledge of the device material, geometry, and fabrication process. The model was then developed by using semiconductor …
Version And Transaction Management In Osmagic: An Object-Oriented Database Implementation Of The Magic Vlsi Layout Design Tool, Gary M. Lightner
Version And Transaction Management In Osmagic: An Object-Oriented Database Implementation Of The Magic Vlsi Layout Design Tool, Gary M. Lightner
Theses and Dissertations
The goal of this thesis was to study the feasibility of using an object-oriented database management system to provide the functionality and performance needed to support a complex computer-aided design tool. We do this by modifying OSMagic, a prototype system of the Magic very large scale integrated (VLSI) circuit design tool implemented on the ObjectStore object- oriented database management system. OSMagic was changed to support three different interfaces to ObjectStore and to work in a networking environment. We then designed and examined the use of version and transaction management models as a means of addressing the weaknesses of the prototype …
A Generic Template Extractor (Gentex) In C For Vlsi Design Verification, Kenneth J. Mcclellan Jr.
A Generic Template Extractor (Gentex) In C For Vlsi Design Verification, Kenneth J. Mcclellan Jr.
Theses and Dissertations
The problem of VLSI design verification through circuit extraction was analyzed. The problems of creating a simple template format, the permutability of pins, maintaining connectivity, and performance were focused on. A generic template extractor (GENTEX) was developed in the C programming language for use as a testbed to find solutions to these problems. Six different extraction algorithms were tested with GENTEX and compared based on performance. EDIF translation programs were used to interface with GENTEX on both the input and output sides. One translation program converted an EDIF representation of a schematic into the template format used by GENTEX. The …
Design And Development Of A High-Speed Winograd Fast Fourier Transform Processor Board, James F. Herron
Design And Development Of A High-Speed Winograd Fast Fourier Transform Processor Board, James F. Herron
Theses and Dissertations
Since 1985, the Air Force Institute of Technology has pursued a project to develop a 4080-point Discrete Fourier Transform processor using the Winograd Fourier Transform Algorithm (WFTA) and Good-Thomas Prime Factoring Algorithm (PFA). In the first attempt to build a working system, this research effort designed and constructed, in part, a modified single processor architecture in order to demonstrate the proof of concept of the WFTA system design. This prototype architecture is simpler in implementation but uses the same principles and procedures as those of the 4080-point WFTA design. The design developed in this thesis was validated using the Very …
Experimental Evaluation Of Incorporating Digital And Analog Integrated Circuit Die On A Common Substrate Utilizing Silicon-Hybrid Wafer-Scale Integration Technology, Philip C. Reamy
Theses and Dissertations
The objective of this research effort was to investigate the implementation of analog circuits in a wafer scale integration system. A test circuit composed of analog and digital subsystems was designed and tested through simulation. IC die containing this test circuit were utilized in the WSI system fabrication. Preliminary investigations were conducted to evaluate the potential improvements to the IC die mounting procedure, a key step in fabricating functional WSI systems. These investigations demonstrated a procedure which produced repeatable results in achieving acceptable planarization of IC die and host substrate surfaces. These investigations also demonstrated the successful application of a …
Hardware-Verification Through Logic Extraction, Michael A. Dukes
Hardware-Verification Through Logic Extraction, Michael A. Dukes
Theses and Dissertations
A Prolog-based system is described which employs logic-extraction to perform hardware-verification. The extraction rules are built automatically from hierarchical structural VHDL models, enabling the equivalence of a structural VHDL description and a layout specification to be verified. Pin-to-pin critical- path analysis is performed within the logic-extraction process; many noncritical paths are pruned early, making pin-to-pin critical path analysis of large circuits feasible. It is demonstrated that a design methodology based on logic extraction, VHDL, and a layout tool can provide a fabricated functionally- correct IC design without circuit-level or switch-level simulation. This methodology is shown to be practical for VLSI …
Design And Analysis Of Electrical Circuits That Produce Fractional-Order Differentiation, Richard N. Hughes
Design And Analysis Of Electrical Circuits That Produce Fractional-Order Differentiation, Richard N. Hughes
Theses and Dissertations
Two half-order differentiator circuit designs were investigated and their electrical performance evaluated (Oldham and Oldfield). Initially, each circuit design was computer modelled and simulated using the HSPICE computer analysis program. Then, each circuit design (Oldham and Oldfield) was fabricated with two different component technologies. This resulted in four circuits, realized on printed circuit boards, to be evaluated--Oldham discrete component; Oldham hybrid component; Oldfield discrete component; and Oldfield surface mount component. The characterizations of each circuit's electrical performance is documented with time, phase, gain, noise and spectrum responses. A comparison of each circuit's performance versus the design criteria and computer model …
An Object-Oriented Database Implementation Of The Magic Vlsi Layout Design System, Timothy M. Jacobs
An Object-Oriented Database Implementation Of The Magic Vlsi Layout Design System, Timothy M. Jacobs
Theses and Dissertations
This thesis attempts to prove that the commercially available Object Store data management system provide the performance and functionality necessary to support a complex engineering design system. This is accomplished by modifying the Magic VLSI circuit layout design system to eliminate its current Unix file data management system and replace it with Object Store. The approach to this research effort includes a design recovery of the Magic system and identification of its ket data management functions. These functions are then modified to take advantage of the database management facilities of Object Store. Additional code is added to instrument performance measurement …
An Investigation Of A Design For A Finite-Difference Time Domain (Fdtd) Hardware Accelerator, James R. Marek
An Investigation Of A Design For A Finite-Difference Time Domain (Fdtd) Hardware Accelerator, James R. Marek
Theses and Dissertations
This study investigated increasing the speed of Finite-Difference Time Domain (FDTD) cell calculations through a special purpose architecture using Very Large Scale Integration (VLSI). These FDTD cell equations model inhomogeneous, isotropic, lossy magnetic and dielectric materials. Special attention was given to simplicity and performance, using the fastest components generally available in AFIT VLSI programs, while attempting to minimize component count. A VHSIC Hardware Description Language simulation of the proposed chip established design feasibility and provided performance estimates: 350 ns to generate the first cell value, 200 ns thereafter (30 MFLOPS maximum double-precision). This study also implemented boundary conditions in hardware …
A Prolog System For Converting Vhdl-Based Models To Generalized Extraction System (Ges) Rules, Michael A. Dukes, Frank M. Brown, Joanne E. Degroat
A Prolog System For Converting Vhdl-Based Models To Generalized Extraction System (Ges) Rules, Michael A. Dukes, Frank M. Brown, Joanne E. Degroat
AFIT Documents
With the advent of VHDL accurate documentation of hardware designs is a practical reality. In the past, schematics were typically used for documentation of hardware designs. However, these schematics would usually become obsolete as the hardware design was being constructed. Deviations in the hardware design would sometimes not be reflected in the schematics. For design groups, failure to update schematics could lead to different parts of a hardware design becoming incompatible. A system to ensure compliance of hardware with its VHDL documentation is presented in this paper. The system, vhdl2ges, is meant to help guide the development of hardware by …
A Vision System Model, Erik J. Fretheim
A Vision System Model, Erik J. Fretheim
Theses and Dissertations
This dissertation provides four major contributions to the field of vision research. The first contribution is a general vision system model. The model, which blends biological as well as technological methods into a coherent approach to vision, will provide a basis for implementing vision systems. The second contribution of this dissertation is to demonstrate particular implementations of portions of the model. These implementations will include methods for using Gabor wavelets in edge detection, in preprocessing images for use as feature vectors in backpropagation neural networks, and as basis functions in a recognition/reconstruction network, as well as methods for integrating color …
A Robotic Tactile Sensor Incorporating Silicon Planar Technology: A Piezoelectric Polyvinylidene Fluoride Film, And On-Chip Signal Processing, Robert C. Fitch Jr.
A Robotic Tactile Sensor Incorporating Silicon Planar Technology: A Piezoelectric Polyvinylidene Fluoride Film, And On-Chip Signal Processing, Robert C. Fitch Jr.
Theses and Dissertations
This research effort pursued the design, fabrication, and test of a robotic tactile sensor. The VLSI integrated circuit (IC) portion of the sensor included a 7 x 7 array of metal electrodes which were individually connected to identical MOSFET amplifiers. A 25 micrometers thick patch (6 mm x 6 mm) of piezoelectric polyvinylidene fluoride (PVDF) film was attached to the array with a non-conductive adhesive, thereby creating an array of taxels. Charge, generated by the PVDF film, was detected by the amplifiers. The outputs of these amplifiers were connected to onchip signal circuitry designed to produce a single stream of …
Design And Fabrication Of An Implantable Cortical Semiconductor Integrated Circuit Electrode Array, Pierre K. Lefevre
Design And Fabrication Of An Implantable Cortical Semiconductor Integrated Circuit Electrode Array, Pierre K. Lefevre
Theses and Dissertations
This research furthered the processing steps of the AFIT 16 by 16 implantable cortical semiconductor integrated circuit electrode array, or brain chip. The areas of interest include the brain chip electron ics, metallization, ionic permeation, and implantation. The electronics and metallization are heavily covered. A high speed, single clock divide-by-two circuit was modified with a reset transistor and cascaded to form a ripple counter. This device had stable operation at specific source voltage and clock voltage and frequency. A 7-stage inverter with 10 unmodified divide-by-two circuits cascaded operated between 1.7 and 8 volts, and between 39 Khz and 1 Mhz, …