VLSI and Circuits, Embedded and Hardware Systems Commons^™

Expanding Temperature Sensing For The Orion Bms 2, Samuel J. Parker

University Honors Theses

Formula SAE (FSAE) is an annual collegiate design competition that takes place across the globe. Portland State University’s team, Viking Motorsports, was committed to designing an Electric Vehicle (EV) for the 2021 FSAE competition. The team designed a completely custom lithium-ion cell battery that is managed by an Orion BMS 2 battery management system. The FSAE rulebook requires a robust temperature monitoring system for any EV power supply. The Orion BMS 2 can only directly collect data from eight temperature sensors, which is not enough to meet FSAE regulation. However, the BMS can be configured to monitor many more sensors …

Laser As A Tool To Study Radiation Effects In Cmos, Bahar Ajdari

Dissertations and Theses

Energetic particles from cosmic ray or terrestrial sources can strike sensitive areas of CMOS devices and cause soft errors. Understanding the effects of such interactions is crucial as the device technology advances, and chip reliability has become more important than ever. Particle accelerator testing has been the standard method to characterize the sensitivity of chips to single event upsets (SEUs). However, because of their costs and availability limitations, other techniques have been explored. Pulsed laser has been a successful tool for characterization of SEU behavior, but to this day, laser has not been recognized as a comparable method to beam …

Synthesis Of Linear Reversible Circuits And Exor-And-Based Circuits For Incompletely Specified Multi-Output Functions, Ben Schaeffer

Dissertations and Theses

At this time the synthesis of reversible circuits for quantum computing is an active area of research. In the most restrictive quantum computing models there are no ancilla lines and the quantum cost, or latency, of performing a reversible form of the AND gate, or Toffoli gate, increases exponentially with the number of input variables. In contrast, the quantum cost of performing any combination of reversible EXOR gates, or CNOT gates, on n input variables requires at most O(n^₂/log₂n) gates. It was under these conditions that EXOR-AND-EXOR, or EPOE, synthesis was developed.

In this …

Early Layout Design Exploration In Tsv-Based 3d Integrated Circuits, Mohammad Abrar Ahmed

Dissertations and Theses

Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during …

Quadded Gasp: A Fault Tolerant Asynchronous Design, Kristopher S. Scheiblauer

Dissertations and Theses

As device scaling continues, process variability and defect densities are becoming increasingly challenging for circuit designers to contend with. Variability reduces timing margins, making it difficult and time consuming to meet design specifications. Defects can cause degraded performance or incorrect operation resulting in circuit failure. Consequently test times are lengthened and production yields are reduced.

This work assess the combination of two concepts, self-timed asynchronous design and fault tolerance, as a possible solution to both variability and defects. Asynchronous design is not as sensitive to variability as synchronous, while fault tolerance allows continued functional operation in the presence of defects. …

Data Driven Feed Forward Adaptive Testing, Chaitrali Santosh Chandorkar

Dissertations and Theses

Test cost is a critical component in the overall cost of the product. Test cost varies in direct proportion with test time. This thesis introduces a data driven feed forward adaptive technique for reducing test time at wafer sort while maintaining the product defect level. Test data from first insertion of wafer is statistically analyzed to make a decision about adaptive test flow at subsequent insertions.

The data driven feed forward technique uses a statistical screen to analyze test data from first probe of wafer and provides recommendations for test elimination at second insertions. At the second insertion dies are …

Static Compaction Of Test Sequences For Synchronous Sequential Circuits, Lijie Qi

Dissertations and Theses

Today, VLSI design has progressed to a stage where it needs to incorporate methods of testing circuits. The Automatic Test Pattern Generation (ATPG) is a very attractive method and feasible on almost any combinational and sequential circuit.

Currently available automatic test pattern generators (ATPGs) generate test sets that may be excessively long. Because a cost of testing depends on the test length, compaction techniques have been used to reduce that length. The motivation for studying test compaction is twofold. Firstly, by reducing the test sequence length, the memory requirements during the test application and the test application time are reduced. …

The Evaluation Of Device Model Dependence In The Design Of A High-Frequency, Analog, Cmos Transconductance-C Filter, Susan Rose Brotman

Dissertations and Theses

It is important to have the ability to predict the effects of device model variation when designing integrated transconductance-C type active filters. Applying these filters to integrated circuit design has become increasingly popular due to its ease of implementation in monolithic form. With the introduction of fully automated design tools, predictable behavior of high-level variables becomes still more important. The purpose of this study is to evaluate the process parameter spread of analog device models to determine the effect on the design parameters of an active filter. This information's significant contribution directly effects the feasibility and realization of automating analog …