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VLSI and Circuits, Embedded and Hardware Systems Commons™

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1992

Articles 1 - 9 of 9

Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems

Version And Transaction Management In Osmagic: An Object-Oriented Database Implementation Of The Magic Vlsi Layout Design Tool, Gary M. Lightner Dec 1992

Version And Transaction Management In Osmagic: An Object-Oriented Database Implementation Of The Magic Vlsi Layout Design Tool, Gary M. Lightner

Theses and Dissertations

The goal of this thesis was to study the feasibility of using an object-oriented database management system to provide the functionality and performance needed to support a complex computer-aided design tool. We do this by modifying OSMagic, a prototype system of the Magic very large scale integrated (VLSI) circuit design tool implemented on the ObjectStore object- oriented database management system. OSMagic was changed to support three different interfaces to ObjectStore and to work in a networking environment. We then designed and examined the use of version and transaction management models as a means of addressing the weaknesses of the prototype …

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A Generic Template Extractor (Gentex) In C For Vlsi Design Verification, Kenneth J. Mcclellan Jr. Dec 1992

A Generic Template Extractor (Gentex) In C For Vlsi Design Verification, Kenneth J. Mcclellan Jr.

Theses and Dissertations

The problem of VLSI design verification through circuit extraction was analyzed. The problems of creating a simple template format, the permutability of pins, maintaining connectivity, and performance were focused on. A generic template extractor (GENTEX) was developed in the C programming language for use as a testbed to find solutions to these problems. Six different extraction algorithms were tested with GENTEX and compared based on performance. EDIF translation programs were used to interface with GENTEX on both the input and output sides. One translation program converted an EDIF representation of a schematic into the template format used by GENTEX. The …

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On The Difficulty Of Manhattan Channel Routing, Ronald I. Greenberg, Joseph Jaja, Sridhar Krishnamurthy Dec 1992

On The Difficulty Of Manhattan Channel Routing, Ronald I. Greenberg, Joseph Jaja, Sridhar Krishnamurthy

Computer Science: Faculty Publications and Other Works

We show that channel routing in the Manhattan model remains difficult even when all nets are single-sided. Given a set of n single-sided nets, we consider the problem of determining the minimum number of tracks required to obtain a dogleg-free routing. In addition to showing that the decision version of the problem isNP-complete, we show that there are problems requiring at least d+Omega(sqrt(n)) tracks, where d is the density. This existential lower bound does not follow from any of the known lower bounds in the literature.

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Design And Development Of A High-Speed Winograd Fast Fourier Transform Processor Board, James F. Herron Dec 1992

Design And Development Of A High-Speed Winograd Fast Fourier Transform Processor Board, James F. Herron

Theses and Dissertations

Since 1985, the Air Force Institute of Technology has pursued a project to develop a 4080-point Discrete Fourier Transform processor using the Winograd Fourier Transform Algorithm (WFTA) and Good-Thomas Prime Factoring Algorithm (PFA). In the first attempt to build a working system, this research effort designed and constructed, in part, a modified single processor architecture in order to demonstrate the proof of concept of the WFTA system design. This prototype architecture is simpler in implementation but uses the same principles and procedures as those of the 4080-point WFTA design. The design developed in this thesis was validated using the Very …

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Minimum Separation For Single-Layer Channel Routing, Ronald I. Greenberg, F. Miller Maley Sep 1992

Minimum Separation For Single-Layer Channel Routing, Ronald I. Greenberg, F. Miller Maley

Computer Science: Faculty Publications and Other Works

We present a linear-time algorithm for determining the minimum height of a single-layer routing channel. The algorithm handles single-sided connections and multiterminal nets. It yields a simple routability test for single-layer switchboxes, correcting an error in the literature.

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Experimental Evaluation Of Incorporating Digital And Analog Integrated Circuit Die On A Common Substrate Utilizing Silicon-Hybrid Wafer-Scale Integration Technology, Philip C. Reamy Mar 1992

Experimental Evaluation Of Incorporating Digital And Analog Integrated Circuit Die On A Common Substrate Utilizing Silicon-Hybrid Wafer-Scale Integration Technology, Philip C. Reamy

Theses and Dissertations

The objective of this research effort was to investigate the implementation of analog circuits in a wafer scale integration system. A test circuit composed of analog and digital subsystems was designed and tested through simulation. IC die containing this test circuit were utilized in the WSI system fabrication. Preliminary investigations were conducted to evaluate the potential improvements to the IC die mounting procedure, a key step in fabricating functional WSI systems. These investigations demonstrated a procedure which produced repeatable results in achieving acceptable planarization of IC die and host substrate surfaces. These investigations also demonstrated the successful application of a …

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Hardware-Verification Through Logic Extraction, Michael A. Dukes Mar 1992

Hardware-Verification Through Logic Extraction, Michael A. Dukes

Theses and Dissertations

A Prolog-based system is described which employs logic-extraction to perform hardware-verification. The extraction rules are built automatically from hierarchical structural VHDL models, enabling the equivalence of a structural VHDL description and a layout specification to be verified. Pin-to-pin critical- path analysis is performed within the logic-extraction process; many noncritical paths are pruned early, making pin-to-pin critical path analysis of large circuits feasible. It is demonstrated that a design methodology based on logic extraction, VHDL, and a layout tool can provide a fabricated functionally- correct IC design without circuit-level or switch-level simulation. This methodology is shown to be practical for VLSI …

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Design And Analysis Of Electrical Circuits That Produce Fractional-Order Differentiation, Richard N. Hughes Mar 1992

Design And Analysis Of Electrical Circuits That Produce Fractional-Order Differentiation, Richard N. Hughes

Theses and Dissertations

Two half-order differentiator circuit designs were investigated and their electrical performance evaluated (Oldham and Oldfield). Initially, each circuit design was computer modelled and simulated using the HSPICE computer analysis program. Then, each circuit design (Oldham and Oldfield) was fabricated with two different component technologies. This resulted in four circuits, realized on printed circuit boards, to be evaluated--Oldham discrete component; Oldham hybrid component; Oldfield discrete component; and Oldfield surface mount component. The characterizations of each circuit's electrical performance is documented with time, phase, gain, noise and spectrum responses. A comparison of each circuit's performance versus the design criteria and computer model …

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Finding A Maximum-Density Planar Subset Of A Set Of Nets In A Channel, Ronald I. Greenberg, Jau-Der Shih Feb 1992

Finding A Maximum-Density Planar Subset Of A Set Of Nets In A Channel, Ronald I. Greenberg, Jau-Der Shih

Computer Science: Faculty Publications and Other Works

We present efficient algorithms to find a maximum-density planar subset of n 2-pin nets in a channel. The simplest approach is to make repeated usage of Supowit's dynamic programming algorithm for finding a maximum-size planar subset, which leads to O(n^3) time to find a maximum-density planar subset. But we also provide an algorithm whose running time is dependent on other problem parameters and is often more efficient. A simple bound on the running time of this algorithm is O(nlgn+n(t+1)w), where t is the number of two-sided nets, and w is the number of nets in the output. Though the worst-case …

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