VLSI and Circuits, Embedded and Hardware Systems Commons^™

An Energy- And Area- Efficient Two-Stage Latch Comparator Using Common-Mode Reset, Larry Yu

Electrical Engineering Theses and Dissertations

This thesis presents an energy-and-area-efficient two-stage comparator implemented in TSMC 65 nm CMOS that incorporates a Floating Inverter Amplifier (FIA) followed by a latch using a common-mode reset scheme. The FIA improves input sensitivity and reduces kickback noise by isolating the input nodes from large latch voltage swings. The proposed latch resets its output nodes to a common-mode voltage rather than one of its supply rails, thereby reducing switching energy during the reset phase. The comparator can resolve differential input voltages as small as 2 mV with a clock period of 500 ps, achieving 74.33 μV input-referred noise while consuming …

Statistical Monitoring Of Hard Faults In Digital Systems, Dany Akshay Deep Isukapalli

Electrical Engineering Theses and Dissertations

Achieving a high test coverage is crucial for helping to ensure that integrated circuits are working correctly and are non-defective. Although scan-based structural tests are used throughout the industry, high-level functional tests may be needed to detect some defects— especially those that are environmentally sensitive. Unfortunately, the character of functional test makes it difficult to obtain high coverage, and it is even hard to estimate coverage because fault simulation times of large circuits are long. As a result, some method is required for predicting the ability of a functional test that has not been fault simulated to detect defects. In …

New Improvements To Defend Against Power Analysis Attacks In Ijtag Access Protocol, Haoran Wei

Computer Science and Engineering Theses and Dissertations

More and more instruments are now integrated on the chip for testing, debugging, monitoring, and post-silicon validation. IEEE Std 1687 (IJTAG) provides efficient access to these instruments. At the same time, techniques for an attacker to steal important data through the IJTAG network have also emerged. To improve the security of the IJTAG network and especially the communication between software and a board, others have proposed a security access protocol with several possible implementations based on an information hiding method. For example, one version of this previously published bidirectional authentication access protocol uses multiple templates to embed keys to improve …

Towards Multipronged On-Chip Memory And Data Protection From Verification To Design And Test, Senwen Kan, Jennifer Dworak

Computer Science and Engineering Theses and Dissertations

Modern System on Chips (SoCs) generally include embedded memories, and these memories may be vulnerable to malicious attacks such as hardware trojan horses (HTHs), test access port exploitation, and malicious software. This dissertation contributes verification as well as design obfuscation solutions aimed at design level detection of memory HTH circuits as well as obfuscation to prevent HTH triggering for embedded memory during functional operation. For malicious attack vectors stemming from test/debug interfaces, this dissertation presents novel solutions that enhance design verification and securitization of an IJTAG based test access interface. Such solutions can enhance SoC protection by preventing memory test …

Enhanced Design For Testability Circuitry For Test, Hui Jiang

Electrical Engineering Theses and Dissertations

More stringent defect detection requirements have led to the creation of new fault models, such as the cell-aware fault model, that attempts to model defects that might be missed by traditional test sets. Unfortunately, the resulting test sets can be long, and thus we have previously explored a DFT-based (Design for Testability-based) approach to reduce test time by harnessing scan shift cycles for cell-aware defect detection. This approach uses a MISR (Multiple Input Signature Register) structure to capture data on the functional inputs to selected scan flip-flops during the shifting procedure. The final signature in the MISR can then be …

Machine Learning Approach To Stability Analysis Of Semiconductor Memory Element, Ravindra Thanniru, Gautam Kapila, Nibhrat Lohia

SMU Data Science Review

Memory stability analysis traditionally relied heavily on circuit simulation-based approaches that run Monte Carlo (MC) analysis over various manufacturing and use condition parameters. This paper researches application of Machine Learning approaches for memory element failure analysis which could mimic simulation-like accuracy and minimize the need for engineers to rely heavily on simulators for their validations. Both regressor and classifier algorithms are benchmarked for accuracy and recall scores. A high recall score implies fewer escapes of fails to field and is the metric of choice for comparing algorithm. The paper identifies that recall score in excess of 0.97 can be achieved …

A 12-Bit 1gs/S Sar-Assisted Pipeline Adc With Harmonic Injecting Residue Amplifier, Liang Fang

Electrical Engineering Theses and Dissertations

Advanced wireless applications require a medium resolution Radio Frequency (RF) sampling Analog to Digital Converter (ADC). By performing sampling of ADC at RF frequency, the mixer and Intermediate Frequency (IF) amplifier can be implemented in the digital domain, which helps the receiver eliminate troublesome mixing spurs and potentially improves the software-defined ratio of the entire system. By combing the merits of the energy-efficient Successive Approximation Register (SAR) ADC and the high-speed pipeline ADC, the SAR-assisted pipeline ADC achieves superior performance in high-speed medium-resolution ADC. However, with the advance of the process, due to the pure analog implementation, the residue amplifier …

A 2.56 Gbps Serial Wireline Transceiver That Supports An Auxiliary Channel And A Hybrid Line Driver To Compensate Large Channel Loss, Xiaoran Wang

Electrical Engineering Theses and Dissertations

Serial transceiver links are widely used for high-speed point-to-point communications. This dissertation describes two transceiver link designs for two different applications.

In serial wireline communications, security is an increasingly important factor to concern. Securing an information processing system at the application and system software layers is regarded as a necessary but incomplete defense against the cyber security threats. In this dissertation, an asynchronous serial transceiver that is capable of transmitting and receiving an auxiliary data stream concurrently with the primary data stream is described. The transceiver instantiates the auxiliary data stream by modulating the phase of the primary data without …

Heuristic-Based Threat Analysis Of Register-Transfer-Level Hardware Designs, Wesley Layton Ellington

Electrical Engineering Theses and Dissertations

The development of globalized semiconductor manufacturing processes and supply chains has lead to an increased interest in hardware security as new types of hardware based attacks, called hardware Trojans, are being observed in industrial and military electronics. To combat this, a technique was developed to help analyze hardware designs at the register-transfer-level (RTL) and locate points of interest within a design that might be vulnerable to attack. This method aims to eventually enable the creation of an end-to-end design hardening solution that analyzes existing designs and suggests countermeasures for potential Trojan attacks. The method presented in this work uses a …

Investigating The Effect Of Detecting And Mitigating A Ring Oscillator-Based Hardware Trojan, Lakshmi Ramakrishnan

Electrical Engineering Theses and Dissertations

The outsourcing of the manufacturing process of integrated circuits to fabrications plants all over the world has exposed these chips to several security threats, especially at the hardware level. There have been instances of malicious circuitry, such as backdoors, being added to circuits without the knowledge of the chip designers or vendors. Such threats could be immensely powerful and dangerous against confidentiality, among other vulnerabilities.

Defense mechanisms against such attacks have been probed and defense techniques have been developed. But with the passage of time, attack techniques have improved immensely as well. From directly observing the inputs or outputs, adversaries …

High-Speed Single-Channel Sar Adc Using Coarse And Fine Comparators With Background Comparator Offset Calibration, Guanhua Wang

Electrical Engineering Theses and Dissertations

A 1-GS/s 8-bit single-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) using coarse and fine comparators with fully background comparator offset calibration is presented. Low-power coarse comparators and low-noise fine comparators are both employed to improve the comparator power efficiency. Non-binary digital-to-analog converter (DAC) with redundancy is employed to tolerate possible errors in the most-significant-bit (MSB) decisions. A novel comparator offset calibration scheme is proposed to remove the offsets between the different comparators, without slowing down the speed of the SAR conversion. The prototype ADC is simulated in a 28 nm CMOS technology and achieves an SNDR of 42.13 dB near Nyquist …

A Low Power High Speed Mobile Memory I/O Interface Using Reconfigurable Multi-Band Multi-Modulation Signaling, Yue Yu

Electrical Engineering Theses and Dissertations

This research mainly focuses on the design of a novel memory I/O interface with high bandwidth and high energy-efficient for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed memory I/O interface, exploiting multi-modulation and multi-band signaling, is capable of supporting simultaneous bidirectional data transition of 4 separate data streams across a single-ended off-chip transmission line to achieve both high speed data rate and low power consumption. This multi-band multi-modulation interface (MMI) consists of multiple RF-band transceivers which utilize ASK modulation, and baseband transceivers which utilize 4-PAM modulation to increase the …

Securing Database Users From The Threat Of Sql Injection Attacks, Nisharg Shah

Electrical Engineering Theses and Dissertations

In the 21^st century, there has been a significant rise in dependency on the Internet for daily activities. Web applications such as online banking, web-based emails, social networking, and many more services have become an instant means of communication. These web applications and the data to which they have access are often targeted using malicious attacks, including SQL (Structured Query Language) Injection Attacks (from now on referenced as SQLIAs), which may cause serious damage. In particular, attackers use SQLIAs to target interactive web applications that incorporate database services. In a SQLIA, an attacker can insert malicious SQL code as …

Genetic Algorithms Vs. Simulated Annealing: A Comparison Of Approaches For Solving The Circuit Partitioning Problem, Theodore W. Manikas, James T. Cain

Computer Science and Engineering Research

An important stage in circuit design is placement, where components are assigned to physical locations on a chip. A popular contemporary approach for placement is the use of simulated annealing. While this approach has been shown to produce good placement solutions, recent work in genetic algorithms has produced promising results. The purpose of this study is to determine which approach will result in better placement solutions.

A simplified model of the placement problem, circuit partitioning, was tested on three circuits with both a genetic algorithm and a simulated annealing algorithm. When compared with simulated annealing, the genetic algorithm was found …