VLSI and Circuits, Embedded and Hardware Systems Commons^™

An Inertial Measurement System For Hand And Finger Tracking, Edward Nelson Henderson

Boise State University Theses and Dissertations

The primary Human Computer Interfaces (HCI) today are the keyboard and mouse. These interfaces do not facilitate a fluid flow of thought and intent from the operator to the computer. A computer mouse provides only 2 Degrees of Freedom (2DOF). Touch interfaces also provide 2DOF, but with multiple points, making the touch interface far more expressive. The hand has 6 Degrees of Freedom (6DOF)by itself. Combined with the motion of the fingers, the hand has the potential to represent a vast array of differing gestures. Hand gestures must be captured before they can be used as a HCI. Fortunately, advances …

Auto-Tuning Antenna, John Chen, Jennifer Tighe

Electrical Engineering

Radio transmitters and antennas have differing impedances at the output and feedpoint, depending on frequency. Modern antenna tuning methods involve manual or automatic resistance and reactance network adjustment to match transmitter and antenna impedance. This reduces power reflections to the transmitter, but introduces losses and prevents full transmitter power from being radiated at the antenna. This project utilizes a variable length antenna element to tune and match transmitter and antenna impedances, allowing efficient power transfer to the antenna. The antenna length varies from 0 to 30.5 inches. The method involves an RF signal with a maximum power of 2 watts …

A 2-D Processor Array For Massively Parallel Image Processing, Anantha Krishna Nelliparthi

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

The concept of introducing image processing logic within the spatial gaps of an array of photodiodes is the key factor behind the presented work. A two-dimensional massively parallel image processing paradigm based on 8X8 pixel neighborhood digital processors has been designed. A low complexity processor array architecture along with its instruction set has been designed and fully verified on a FPGA platform. Various image processing tests have been run on the FPGA platform to demonstrate the functionality of a design that uses 12 parallel processors. The test results indicate that the architecture is scalable to support high frame rates while …

Investigation Of A Floating Load Buck Dc-Dc Switching Converter, Hong Tan

Graduate Theses and Dissertations

A floating load buck DC-DC switching converter was analyzed, simulated, designed and prototyped. The floating load buck converter is first compared to the conventional buck converter. It was found that both the floating load buck converter and conventional buck converter exhibit similar conversion characteristics despite the differences in the placement of their output inductors. A floating load buck converter was designed to be used as a high-voltage off-line light-emitting diodes (LEDs) driver using a Texas Instruments' TPS92001 controller. Finally, the characteristics of this floating load buck converter LED driver were experimentally examined.

Full Custom Vlsi Design Of On-Line Stability Checkers, Chris Y. Lee

Master's Theses

A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.

A method for concurrent fault testing called On-line Stability Checking …

Wireless Embedded Smart Cameras: Performance Analysis And Their Application To Fall Detection For Eldercare., Alvaro Pinto

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

Wireless Embedded Smart Camera Networks has received a lot of attention from academia and industry because they are small in size and easy to deploy, and they offer a multitude of attractive applications. They can be used for embedded single unit applications, or can be networked for multi-camera applications.

We first analyze three different operation scenarios for a wireless vision sensor network wherein different levels of local processing is performed. A detailed quantitative comparison of three operation scenarios are presented in terms of energy consumption and latency. This quantitative analysis provides the motivation for performing high-level local processing and decision …

Discrete Alarm Clock, Travis Moore, Collin Barth

Electrical Engineering

The standard alarm clock, as used daily by millions worldwide, has clear room for modification and improvement.  This paper documents an implementation that rectifies many of these flaws.  Improvements include adjustable snooze length, an IR remote for ease of use, and an RF headset for discrete alarm use or potential incorporation into a device much like a hearing aid.  The processes involved in creating a digital alarm clock, as well as the obstacles met in the implementation of the enhanced design, are detailed within.

Mp3 Player System Design, Eric Wu

Electrical Engineering

The purpose of this project is to design and build a portable audio player that reads music files off an SD card, decodes the music file and outputs the music through a headphone jack.  A microcontroller running FreeRTOS will facilitate the data transfer between an SD card and the decoding chip.  The decoded audio will then be sent to a high-end DAC chip that outputs the sound.

Laser Cursor, Michael Liman

Electrical Engineering

A user controls a cursor on a computer screen using a laser pointer.  A camera picks up the laser pointer’s position and sends the data to the computer to move the cursor in the correct position.

Controller Board Prototype Development For The Cal Poly Super Project, Clifford Susa

Electrical Engineering

Now in phase two of development, the Cal Poly Sustainable Power for Electrical Reources (SuPER) project will provide power to families for an estimated lifespan of 20 years at a cost of $500. Phase two of the SuPER project looks at implementing microcontrollers to monitor the health and status of the system. This senior project looks specifically at the performances of the SuPER Controller which communicates with the SuPER Digitizer to gather data such as voltage, current, temperature, and power. An SD memory card will store this data, and to view this data, then download to a PC.

Project 308: Augmented Reality Mario Kart, Joseph Abad, David Allender, Joryl Calizo, Ryan Gaspar, Gavin Lee

Computer Engineering

Mario Kart is a popular go-kart racing game developed by Nintendo. The premise of the game is simple: drive a go-kart along a racetrack and reach the finish line before the other players. What makes this game unique, however, is the inclusion of weapons, traps, and other projectiles that a player can use to gain an advantage in the race. We have taken on the challenge of not only recreating this amazing game, but using the art of Augmented Reality to fully immerse the player in the full experience. Rather than play the game on a television screen with a …

Low-Power, High-Bandwidth And Ultra-Small Memory Module Design, Qawi Ibnzayd Harvard

Boise State University Theses and Dissertations

The main memory subsystem has become inefficient. The performance gained has come at the expenses of power consumption, capacity, and cost. This dissertation proposes novel module, DRAM, and interconnect architectures in an attempt to alleviate these trends. The proposed architectures utilize low-cost interconnects and packaging innovations to substantially reduce the power, and increase the capacity and bandwidth of the main memory system.

This dissertation develops the theory behind a low-cost packaging technology to create an 8-die and 32-die memory module. The 32-die memory module measures less than 2 cm³.

This dissertation also proposes a 4 Gb DRAM architecture …

Increasing Efficiency In Boundary Security With Wireless Sensor Networks And Geospatial Information Systems Using Homology Theory, Luis Berumen^, Eric Chaidez^, Hamide Dogan*, Jose Gerardo Rosiles**

COURI Symposium Abstracts, Spring 2011

As part of an institutional investigation, we attempt to address the challenges the US customs and Border protection agency faces in the El Paso region. Our research focuses on defining a system for the surveillance application, and the use of mathematical models employed to achieve a greater efficiency of such architecture. With the use of the defined system, we apply homology theory through the algebraic process of topology, to accomplish an independent coordinate-free based system, which covers the surveillance area, with lesser quantity of sensor nodes. Our architecture makes the use of an operating system for wireless sensor networks; TinyOS, …

Dynamic Polymorphic Reconfiguration To Effectively “Cloak” A Circuit’S Function, Jeffrey L. Falkinburg

Theses and Dissertations

Today's society has become more dependent on the integrity and protection of digital information used in daily transactions resulting in an ever increasing need for information security. Additionally, the need for faster and more secure cryptographic algorithms to provide this information security has become paramount. Hardware implementations of cryptographic algorithms provide the necessary increase in throughput, but at a cost of leaking critical information. Side Channel Analysis (SCA) attacks allow an attacker to exploit the regular and predictable power signatures leaked by cryptographic functions used in algorithms such as RSA. In this research the focus on a means to counteract …

Evaluation Of The Single Keybit Template Attack, Eric W. Garcia

Theses and Dissertations

Side Channel leakage is a serious threat to secure devices. Cryptographic information extraction is possible after examining any one of the various side channels, including electromagnetic. This work contributes a new method to achieve such a purpose. The Single Keybit Template Attack (SKTA) is introduced as a means to extract encryption keys from embedded processors and other integrated circuit devices performing DES encryptions by passively monitoring and exploiting unintentional RF emissions. Key extraction is accomplished by creating two templates for each bit value of the key based on instantaneous amplitude responses as a device executes DES operations. The resultant templates …

Multicore, Multithreaded, Phase-Synchronous Fm Sound Synthesizer, Justin Tomlin

Electrical Engineering

This project implements a phase-synchronous FM synthesis algorithm in hardware.  Envelope and low frequency oscillator modulation of oscillator parameters is implemented.  The microcontroller the system is based on, the XMOS XS1-G4, allows for physical parallelism including features such as multiple cores, multiple hardware threads on each core, a hardware event-driven thread scheduler, and channel, channel ends, and link switches for thread and core communication.  The event-driven architecture of this device was ideal for implementing this synthesis algorithm.  The final product is portable, durable, has a simple, intuitive user interface, and allows for extensive spectral shaping capabilities.  The basic functional requirements …

Parameterizable Network-On-Chip Emulation Framework, Jaya Suseela

UNLV Theses, Dissertations, Professional Papers, and Capstones

Networks-on-Chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. But there is no public accessible HDL synthesizable NoC framework which connects industrial level cores and runs real applications on them. Moreover, many challenging research problems remain unsolved at all levels of design abstraction; design exploration of NoC architecture for applications, scheduling and mapping algorithms, evaluation of switching, topology or routing algorithm for efficient execution of application and optimizing communication cost, area, energy etc Solution to solve the above problem calls for the development of synthesizable, parameterizable NoC Framework that would evaluate and implement the above …

A Single-Chip Ultra-Wideband Based Wireless Sensor Network Node, Nathan R. Schemm

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

This dissertation presents the design of a next-generation wireless sensor network node. The node incorporates many new and innovative technologies such as an ultra-wideband radio which allows very low-energy communication, a low-power radiation detection front end, and an efficient implementation of dynamic voltage scaling which improves the energy efficiency of the integrated processor. The complete design is integrated on a single chip for maximum power savings and minimal size.

The ultra-wideband transceiver includes many novel techniques to produce a receiver with low power consumption and fast and accurate packet acquisition and reception. These include the use of a standard symmetric …

Asynchronous Mips Processors: Educational Simulations, Robert L. Webb

Master's Theses

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …

Synthesizing Optimal Fixed-Point Arithmetic For Embedded Signal Processing, Kenneth J. Hass

Faculty Conference Papers and Presentations

No abstract provided.

Polyenvi, Stephen Beard, Josh Engel, Paul Fake, Diego Flores, Alvaro Nunez, Miguel Wong

Electrical Engineering

Poor indoor air quality is a problem that is recognized by the Environmental Protection Agency (EPA) to cause health issues. In order to raise awareness of this problem, this document outlines the construction of a device that economically measures air quality through five metrics: dust, smoke, ozone, humidity, and temperature. The device integrates with a router to provide users access to information about their indoor air quality anywhere over the internet as well as local access to the data via an LCD mounted on the router. By increasing indoor air quality awareness, this device will aid users in making adjustments …

K-Delta-1-Sigma Modulators For Wideband Analog-To-Digital Conversion, Vishal Saxena

Boise State University Theses and Dissertations

As CMOS technology scales, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents, and additional mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in these small processes a first-order K-Delta-1-Sigma (KD1S) modulator-based ADC was proposed. The KD1S topology employs inherent time-interleaving with a shared integrator and K-quantizing feedback paths and can potentially achieve significantly higher conversion bandwidths when compared to the traditional …

Global Positioning Logger, Matthew Hall

Computer Engineering

The Global Positioning Logger (GPL) is a mobile embedded device that utilizes GPS technology. The GPS data is used to display current speed and past global locations.

Design Techniques To Improve Time Dependent Dielectric Breakdown Based Failure For Cmos Circuits, Emanuel S. Tarog

Master's Theses

This project investigates the failure of various CMOS circuits as a result of Time Dependent Dielectric Breakdown (TDDB) and explores design techniques to increase the mean time to failure (MTTF) of large-scale circuits. Time Dependent Dielectric Breakdown is a phenomenon where the oxide underneath the gate degrades as a result of the electric field in the material. Currently, there are few well documented design techniques that can increase lifetime, but with a tool chain I created called the MTTF Analyzing Program, or MAP, I was able to test circuits under various conditions in order to identify weak links, discover relationships, …

High Contrast Grayscale Object Tracking Embedded System Design, Scott Donald Neally

Electrical Engineering

The purpose of this project is to prove that a real-time object-tracking camera can be implemented using the Digilent NEXYS board with Xilinx Platform Studio. With great ambition I set to implement the camera with RGB color tracking of bright green objects. This would make segmentation between the object of interest and its background much easier, allowing less stringent requirements on the background color beyond the object. Because of time restraints, the actual implementation remains as 8-bit grayscale, where the object of interest is intended to be white and highly contrasted from its black background. A simple algorithm is used …

Wide I/O Dram Architecture Utilizing Proximity Communication, Qawi Ibnzayd Harvard

Boise State University Theses and Dissertations

The bandwidth and power consumption of dynamic random access memory, used as the main memory of a computer system, impacts the computer’s execution rate even with the existence of a memory hierarchy. DRAM manufacturers focus on density increases due to the innate price per bit decline of main memory while processor manufacturers continually focus on boosting performance by increasing the number of instructions completed per second. This leads to a performance gap between the microprocessor and DRAM.

Proximity communication promises to increase the I/O density of DRAM products while reducing the power consumption of the main memory system. This thesis …

Phase Change Memory: Array Development And Sensing Circuits Using Delta-Sigma Modulation, Mahesh Balasubramanian

Boise State University Theses and Dissertations

Chalcogenide based non-volatile Phase Change Memory (PCM) circuits were designed to investigate new emerging non-volatile memory technologies. An overview of the operation of chalcogenide-based resistive PCM for circuit designers is presented. MOSIS fabrication service was used along with Idaho Microfabrication Lab at Boise State University to develop PCM chips. Experimental results show successful integration of two discreet processing services for developing chalcogenide based non-volatile memory circuits. Possible multi-state capabilities were observed during the testing of single memory bits.

Four Delta Sigma Modulation (DSM) based sensing techniques for resistive memory are presented. The proposed sensing techniques have the advantage over traditional …

Where Does Your Institution Stand?, Wendell Brase, Mark Askren

Information Technology Services: Publications

Media coverage of sustainability and "green" issues is hard to ignore these days. But less clear is a specific understanding of what this agenda means within higher ed IT organizations. For starters, it's useful to self-assess whether your campus is a leading innovator on all things "green" or satisfied to remain inconspicuous in the middle of the pack. If your institution is trailing but wants to assert a leadership role in environmental stewardship, you need to get engaged to understand what it will take to catch up and how IT can be a leader, not just a contributor, to such …

Removing Redundant Logic Pathways In Polymorphic Circuits, Hanseok Kim

Theses and Dissertations

Evaluating the quality of software and circuit obfuscators is a research goal of great interest. However, there exists little research about evaluation of obfuscation effectiveness through analyzing and investigating redundancies found in the obfuscated variants. In this research, we consider programs represented as structural combinational circuits and then analyze obfuscated variants of those circuits through a tool that produces functionally equivalent variants based on subcircuit selection and replacement. We then consider how Boolean logic and reduction affects the size and levelization of circuit variants, giving us a concrete metric by which to consider obfuscation effectiveness. To accomplish these goals, we …

A Study Of Switched-Capacitor Filters, Kacie Thomas

Electrical Engineering Undergraduate Honors Theses

This paper presents the basic principles of the switched-capacitor circuit. In order to become more acquainted with the workings and design of filters and switched-capacitor filters specifically, an example filter was designed based on a set of parameters. It was constructed starting in the passive stage, then the active stage and finally the switched-capacitor filter was generated. All of these circuits were also simulated using SwitcherCAD and Saber. Then, a switched-capacitor filter designed by Auburn University was redesigned using the same process as the example circuit. It was also simulated in all three stages. The results from this design are …