Digital Circuits Commons^™

Unidirectional Cordic For Efficient Computation Of Trigonometric And Hyperbolic Functions, Satish Ravichandran

Electrical & Computer Engineering Theses & Dissertations

CORDIC (Coordinate Rotation Digital Computer) is an iterative algorithm to compute values of trigonometric, logarithmic and transcendental functions by performing vector rotations, which can be implemented with only shift and add operations in a digital system. CORDIC algorithms are extensively used in the areas of digital signal processing, digital image processing and artificial neural networks. A new technique, named unidirectional CORDIC, for efficient computation of trigonometric and hyperbolic functions is presented in this thesis. In the conventional CORDIC algorithm, the vector rotations are performed in both clockwise and counterclockwise directions, but in the unidirectional CORDIC the vectors are rotated only …

Analysis Of Error Recovery Effects On Digital Flight Control Systems, Arturo Tejada Ruiz

Electrical & Computer Engineering Theses & Dissertations

Life-critical, real-time applications like flight-by-wire aircraft, rely on closed-loop digital control systems and fault-tolerant computer systems to reliably achieve the desired operation. The computer systems, however, may be affected by random hardware/software faults induced mainly by environmental conditions such as high intensity radiated fields (HIRF) and lightning. These harsh electromagnetic environments are known to induce common­ mode faults (CMF) in aircraft electronic systems, which disrupt fault-tolerant provisions and possibly affect the operation of the digital control system. Current flight-by-wire aircraft have computer systems that can neither detect CMF nor recover from them. New systems are under investigation that can recover …

Implementation Of Large Neural Networks Using Decomposition, Henry Selvaraj, H. Niewiadomski, P. Buciak, M. Pleban, Piotr Sapiecha, Tadeusz Luba, Venkatesan Muthukumar

Electrical & Computer Engineering Faculty Research

The article presents methods of dealing with huge data in the domain of neural networks. The decomposition of neural networks is introduced and its efficiency is proved by the authors’ experiments. The examinations of the effectiveness of argument reduction in the above filed, are presented. Authors indicate, that decomposition is capable of reducing the size and the complexity of the learned data, and thus it makes the learning process faster or, while dealing with large data, possible. According to the authors experiments, in some cases, argument reduction, makes the learning process harder.

An Analysis Of A Private-Key Cryptosystem, Wei-Wey Tan

Student Works (2000-2009)

In this dissertation, we have presented a new block cipher. The proposed block cipher is a Substitution-Permutation network cryptosystem with a block length of 128 bits and key length of 256 bits. With the increased key length and block size, the proposed block cipher has greater security over DES. A modular design approach was applied. The cipher has three major building blocks and their interaction has been carefully chosen to achieve better security and performance. Algorithmic S­-Boxes are used to provide confusion and nonlinearity in the cipher. The proposed cipher uses a highly diffusive diffusion layer, which is a combination …

A Vhdl Implementation Of Bist Technique In Uart Design, Mohd. Yamani Idna Idris

Student Works (2000-2009)

No abstract provided.

Rekabentuk Perkakasan Khas Ecc (Reed-Solomon), Muhamad Mursid Noorizan

Student Works (2000-2009)

Dokumen ini disiapknn bagi menyediakan laporan tentang perjalanan projek perkakasan khas ECC yang dijalankan. Bahagian pertama dokumen ini terdapat pengenalan tentang projek. Bahagian kedua pula menyatakan tentang kajian yang telah dilakukan bagi memilih kod-kod pembetulan yang ingin dibangunkan. Seterusnya pada bahagian tiga, dinyatakan serba sedikit tentang bahasa yang digunakan dalam pembangunan projek iaitu VHDL. Sahagian keempat pula menceritakan tentang senibina-senibina dan rekabentuk-rekabentuk perkakasan khas. Dalam bahagian lima, dokumen menceritakan tentang fasa pembangunan yang telah dijalankan. Bahagian enam dan tujuh pula menceritakan tentang perbincangan dan kesimpulan daripada projek yang telah dijalankan.

Pendarab Titik Apungan 32bit Bertalian Paip, Noorzaily Mohamed Noor

Student Works (2000-2009)

Tesis ini menghuraikan sebuah pendarab titik apungan 32bit bertalian paip 18MHz yang direkabentuk menggunakan bahasa perihalan perkakasan YHDL, peralatan sintesis Synopsys FPGA Express dan ·peralatan pemetaan Xilinx Alliance, PTA ini menggunakan 1007 CLB dan 100 10B di mana peranti pemetaan yang digunakan ialah xc4036xl-bg432-2 daripada pustaka XC4000 Xilinx FPGA. Pendarab ini mengandungi tiga tahap talian paip yang belainan fungsi. Tahap pertama melaksanakan penjanaan dedarab dan penambahan dedarab secara carry save dan penambahan eksponen. la menggunakan algoritma Booth tertib kedua dan pepohon Wallace dengan pemampat 4-2. Tahap kcdua pula melakukan penambahan bawaan rambatan akhir, penormalan mantisa dan pembetulan eksponen manakala tahap …

Mekanisma Pengujian Alu Menggunakan Teknik Boundary Scan, Abdul Aziz Ahmad Zaki Zamani

Student Works (2000-2009)

ALU testing mechanism using Boundary Scan technique is a project which is develop to be the tester for testing the digital circuit, integrated circuit and computer chip. The goal of this project is to develop a mechanism and as well building an ALU chip so that we will able to test and determine whether the chips are in a good shape and condition. This project contains two parts: one is lo develop an ALU and second is to develop the boundary scan chip. ALU is a unit or a component for a cligital circuit or a integrated circuit which is …

Litar Aritmetik Reja, Abd. Mutalib Leorna Shazerine

Student Works (2000-2009)

Projek Ilmiah Tahap Akhir II, iaitu WXES 3182 adalah suatu latihan akademik di dalam penyelidikan, rekabentuk, pembangunan dan komunikasi yang melibatkan prinsip-prinsip sains komputer. Projek WXES 3182 ini merupakan kursus pelengkap bagi pelajar-pelajar tahun akhir untuk mendapatkan penganugerahan Sarjana Muda Sains Komputer. Projek WXES 3182 ini adalah kesinabungan daripada projek WXES 3181 Kajian penyehdikan yang telah dijalankan adalah berkaitan dengan konsep sistem nombor reja dan litar aritmetik reja. Laporan latihan ilmiah tahap akhir II ini, merangkumi pembangunan projek WXES 3181 dan WXES 3182. laporan ini terdiri daripada lapan bahagian dan diantaranya ialah pengenalan kepada projek, kajian literasi, metodologi yang digunakan …

Vhdl Description For Ip Engine, Bathich Zeliall

Student Works (2000-2009)

Developing hardware support for network layer protocol processing is a very complex and demanding task. However. for optimal performance hardware acceleration can be required. To cope with the situation. this project present a high-level design approach. which targets the development of configurable and reusable components. Therefore it obtains the integration of advanced tools for the development of the IP Engine into the design environment. This process is illustrated based on a TCP/IP header analysis and validation component for which initial performance results are presented. The development of this Engine is embedded in an approach to develop flexible and configurable protocol …

Intelligent Approaches To Vlsi Routing, Maolin Tang

Theses: Doctorates and Masters

Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As a result, conventional approaches, which have been successfully used to handle relatively small-size routing problems, are not suitable to be used in tackling large-size routing problems because they lead to 'combinatorial explosion' in search space. Hence, there is a need for exploring more efficient routing approaches to be incorporated into today's VLSI routing system. This thesis strives to use intelligent approaches, including symbolic intelligence and computational intelligence, to solve three VLSI routing problems: Three-Dimensional (3-D) …

Implementation And Performance Of Error Correction Codes For High-Speed Computer Networks, Jochen Spengler

Dissertations and Theses

During the transmission of data there is always a possibility that errors occur and some pieces are modified. If the receiver detects an error it either sends a request for retransmission or, like in networks using Ethernet, it does not send an acknowledgment for the erroneous frame. In this case the sender waits a certain time and retransmits the frame. With the development of faster computer networking hardware and the need for more real-time applications, these errors have become a major concern. Long retransmission latencies and the need for large memories for buffering drive the development of more reliable network …

Rapid Prototyping Using Reprogrammable Logic, Jared L. Bell

Honors Capstone Projects and Theses

No abstract provided.

Genetic Algorithms Vs. Simulated Annealing: A Comparison Of Approaches For Solving The Circuit Partitioning Problem, Theodore W. Manikas, James T. Cain

Computer Science and Engineering Research

An important stage in circuit design is placement, where components are assigned to physical locations on a chip. A popular contemporary approach for placement is the use of simulated annealing. While this approach has been shown to produce good placement solutions, recent work in genetic algorithms has produced promising results. The purpose of this study is to determine which approach will result in better placement solutions.

A simplified model of the placement problem, circuit partitioning, was tested on three circuits with both a genetic algorithm and a simulated annealing algorithm. When compared with simulated annealing, the genetic algorithm was found …

Investigation Of Solution Space Of Trees And Dags For Realization Of Combinational Logic In At 6000 Series Fpgas, Philip Ho

Dissertations and Theses

Various tree and Directed Acyclic Graph structures have been used for representation and manipulation of switching functions. Among these structures the Binary Decision Diagrams have been the most widely used in logic synthesis. A BDD is a binary tree graph that represents the recursive execution of Shannon's expansion. A FDD is a directed function graph that represents the recursive execution of Reed Muller expansion.

A family of decision diagrams for representation of Boolean function is introduced in this thesis. This family of Kronecker Functional Decision Diagrams (KFDD) includes the Binary Decision Diagrams (BDD) and Functional Decision Diagrams (FDD) as subsets. …

Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec

Theses and Dissertations

The minimization of logic circuits has been an important area of research for more than a half century. The approaches taken in this field, however, have for the most part been ad hoc. Boolean techniques have been employed to manipulate formulas, but not to perform symbolic reasoning. Boolean equations are employed principally as icons; they are never solved. The first objective of this dissertation is to apply Boolean reasoning systematically and uniformly to the minimization problem. Boolean reasoning entails the reduction of systems of Boolean equations to a single equation; the single equation is an abstraction, independent of the form …

Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau

Theses and Dissertations

VHDL models are executed sequentially in current commercial simulators. As chip designs grow larger and more complex, simulations must run faster. One approach to increasing simulation speed is through parallel processors. This research transforms the behavioral and structural models created by Intermetrics' sequential VHDL simulator into models for parallel execution. The models are simulated on an Intel iPSC/2 hypercube with synchronization of the nodes being achieved by utilizing the Chandy Misra paradigm for discrete-event simulations. Three eight-bit adders, the ripple carry, the carry save, and the carry-lookahead, are each run through the parallel simulator. Simulation time is cut in at …

Electrically Erasable Programmable Integrated Circuits For Replacement Of Obsolete Ttl Logic, Joseph V. Breen

Theses and Dissertations

Two microcircuits with electrically erasable programmable logic arrays, which use Fowler-Nordheim (F-N) tunneling for both programming and erasing, were designed to demonstrate the use of programmable logic for obsolete TTL logic replacement. Each microcircuit was fabricated in the Orbit 2-micron double-poly low noise analog CMOS process through MOSIS. Software to generate VHDL structural models from a pin list was developed and the logic of both designs was verified by simulation using the Zycad VHDL simulator. The first microcircuit included a simple programmable logic circuit and test cells that allowed measurement of the programming characteristics of the floating gate transistors. Test …

Hybrid Wafer Scale Microcircuit Integration -- [ 5008213 ], Edward S. Kolesar Jr.

AFIT Patents

A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and hose wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment …

A Prolog-Based System For Hardware Verification, Kevin L. Sparks

Theses and Dissertations

With the expanding number of components provided on a single digital chip, verification of digital designs is becoming a major problem. The more circuits one places on a single chip, the greater the number of input/output combinations which need to be checked. A paper by Barrow in 1984 discusses a Prolog-based hierarchical formal verification system which he calls VERIFY. Barrow provided a lot of information on what VERIFY can and cannot do, and on projected enhancements. He does not, however, mention how VERIFY actually performs the task of formal verification. This thesis will provide a description of one possible implementation …

Optimal Iterative Task Scheduling For Parallel Simulations, Joann M. Sartor

Theses and Dissertations

The ultimate purpose of this research is to reduce the time needed for execution of parallel computer simulations. In particular, the impact of task assignment strategies is determined for parallel VHDL circuit simulations. The classical scheduling problem, which assigns n precedence-constrained tasks to m processors is NP-complete in all but the simplest cases. The problem of assigning simulation tasks is further complicated by the iterative nature of computer simulations: each task is required to execute multiple times as the simulation executes. This investigation develops a polynomial-time algorithm (the level strategy) which provides optimal assignment for iterative systems with specific constraints. …

Hybrid Wafer Scale Microcircuit Integration -- [ 4989063 ], Edward S. Kolesar Jr.

AFIT Patents

A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and host wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment …

Simple Synchronous Detector For Spectroscopic Studies, Mokhtar Mofidi, M. Keith Hudson, Reagan Cole, James D. Wilson

Journal of the Arkansas Academy of Science

Lock-in-amplifiers are used in many applications for signal processing and offer the ability to discriminate high levels of noise. While these instruments are very powerful and offer many features, they are not portable and are expensive. An economical and easy to use alternative circuit is presented which incorporates pre-amplification, reference, and synchronous detection on one circuit board. The design can be used in laboratory or process control situations where its small size and low cost are advantageous. The circuit was successfully applied to moderate and high level signals as seen in flame infrared emission detection and in a portable radiometer …

Recursive Optimization Of Digital Circuits, John Knutson

Theses and Dissertations

The goal of this thesis is twofold: first, to identify the advantages and disadvantages of existing optimization systems and second, to develop an optimization system that uses Boolean principles to generate a recursive realization of combinational logic. Current multi-level optimization systems fall into two categories: local optimization which removes redundancy by pattern matching on a local scale and global optimization which works with the equations that specify a circuit rather than with the circuit implementation itself. While global systems are very flexible and can produce near-optimal solutions, they are inherently complex. This research effort demonstrates that an effective global optimization …

Specification And Equivalence Verification Of Sequential Circuits Via Vhdl, Richard L. Miller

Theses and Dissertations

This research presents a merger of the specification and design capabilities of the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) with a known verification method (UC Berkeley's verify software) in order to solve the design and verification problem of sequential circuits. The fruits of this research are a behavioral VHDL model for sequential circuit specification, a structural VHDL model for sequential circuit design, and a method for comparing two circuits described using these VHDL models in order to demonstrate circuit equivalence. The behavioral and structural VHDL models were developed and tested within the Intermetric's VHDL software support …

Use Of A Calculator Chip For Realtime Data Processing, Jeffrey O. Cohen, Hal E. Mcloud

Journal of the Arkansas Academy of Science

No abstract provided.

Design Of A Microprocessor Controlled Telecommunication System, George J. Maroutsos

Dissertations and Theses

Recent advancements in Large Scale Integration Technology have made available devices, such as microprocessors, analog gates and "three state" logic, that provide the designer with a wide range of possibilities in the design of telecommunication systems. A microprocessor and analog gates are utilized in this design to demonstrate the feasibility of implementing a flexible Telecommunication System. The microprocessor is programmed to control, through software, the system functions. The feasibility of systems highly adaptable to the needs of individual subscribers is thus demonstrated.