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- Boundary Scan Technic; High speed integration circuit; Digital circuit (1)
- Design and construction (1)
- Floating-Point Multiplier; VHDL; FPGA; Pipelined Architecture; Booth Algorithm; Wallace Tree. (1)
- Integrated circuits (1)
- Litar aritmetik reja; Sains komputer; Sistem nombor reja; pengkodan VHDL; Rajah simulasi (1)
Articles 1 - 5 of 5
Full-Text Articles in Digital Circuits
Pendarab Titik Apungan 32bit Bertalian Paip, Noorzaily Mohamed Noor
Pendarab Titik Apungan 32bit Bertalian Paip, Noorzaily Mohamed Noor
Student Works (2000-2009)
Tesis ini menghuraikan sebuah pendarab titik apungan 32bit bertalian paip 18MHz yang direkabentuk menggunakan bahasa perihalan perkakasan YHDL, peralatan sintesis Synopsys FPGA Express dan ·peralatan pemetaan Xilinx Alliance, PTA ini menggunakan 1007 CLB dan 100 10B di mana peranti pemetaan yang digunakan ialah xc4036xl-bg432-2 daripada pustaka XC4000 Xilinx FPGA. Pendarab ini mengandungi tiga tahap talian paip yang belainan fungsi. Tahap pertama melaksanakan penjanaan dedarab dan penambahan dedarab secara carry save dan penambahan eksponen. la menggunakan algoritma Booth tertib kedua dan pepohon Wallace dengan pemampat 4-2. Tahap kcdua pula melakukan penambahan bawaan rambatan akhir, penormalan mantisa dan pembetulan eksponen manakala tahap …
Mekanisma Pengujian Alu Menggunakan Teknik Boundary Scan, Abdul Aziz Ahmad Zaki Zamani
Mekanisma Pengujian Alu Menggunakan Teknik Boundary Scan, Abdul Aziz Ahmad Zaki Zamani
Student Works (2000-2009)
ALU testing mechanism using Boundary Scan technique is a project which is develop to be the tester for testing the digital circuit, integrated circuit and computer chip. The goal of this project is to develop a mechanism and as well building an ALU chip so that we will able to test and determine whether the chips are in a good shape and condition. This project contains two parts: one is lo develop an ALU and second is to develop the boundary scan chip. ALU is a unit or a component for a cligital circuit or a integrated circuit which is …
Litar Aritmetik Reja, Abd. Mutalib Leorna Shazerine
Litar Aritmetik Reja, Abd. Mutalib Leorna Shazerine
Student Works (2000-2009)
Projek Ilmiah Tahap Akhir II, iaitu WXES 3182 adalah suatu latihan akademik di dalam penyelidikan, rekabentuk, pembangunan dan komunikasi yang melibatkan prinsip-prinsip sains komputer. Projek WXES 3182 ini merupakan kursus pelengkap bagi pelajar-pelajar tahun akhir untuk mendapatkan penganugerahan Sarjana Muda Sains Komputer. Projek WXES 3182 ini adalah kesinabungan daripada projek WXES 3181 Kajian penyehdikan yang telah dijalankan adalah berkaitan dengan konsep sistem nombor reja dan litar aritmetik reja. Laporan latihan ilmiah tahap akhir II ini, merangkumi pembangunan projek WXES 3181 dan WXES 3182. laporan ini terdiri daripada lapan bahagian dan diantaranya ialah pengenalan kepada projek, kajian literasi, metodologi yang digunakan …
Vhdl Description For Ip Engine, Bathich Zeliall
Vhdl Description For Ip Engine, Bathich Zeliall
Student Works (2000-2009)
Developing hardware support for network layer protocol processing is a very complex and demanding task. However. for optimal performance hardware acceleration can be required. To cope with the situation. this project present a high-level design approach. which targets the development of configurable and reusable components. Therefore it obtains the integration of advanced tools for the development of the IP Engine into the design environment. This process is illustrated based on a TCP/IP header analysis and validation component for which initial performance results are presented. The development of this Engine is embedded in an approach to develop flexible and configurable protocol …
Intelligent Approaches To Vlsi Routing, Maolin Tang
Intelligent Approaches To Vlsi Routing, Maolin Tang
Theses: Doctorates and Masters
Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As a result, conventional approaches, which have been successfully used to handle relatively small-size routing problems, are not suitable to be used in tackling large-size routing problems because they lead to 'combinatorial explosion' in search space. Hence, there is a need for exploring more efficient routing approaches to be incorporated into today's VLSI routing system. This thesis strives to use intelligent approaches, including symbolic intelligence and computational intelligence, to solve three VLSI routing problems: Three-Dimensional (3-D) …