Open Access. Powered by Scholars. Published by Universities.®
Articles 1 - 4 of 4
Full-Text Articles in Digital Circuits
System And Method For Identifying Electrical Properties Of Integrate Circuits, Mary Y. Lanzerotti
System And Method For Identifying Electrical Properties Of Integrate Circuits, Mary Y. Lanzerotti
AFIT Patents
A new method for displaying electrical properties for integrated circuit (IC) layout designs provides for improved human visualization of those properties and comparison of as designed layout design parameters to as specified layout design parameters and to as manufactured layout parameters. The method starts with a circuitry as designed layout in a first digital format, extracts values for electrical properties from that circuitry as designed layout then annotates those values back into the first digital format. The annotated circuitry as designed layout is then converted from the first digital format to a second digital format that can be converted to …
Relocatable Field Programmable Gate Array Bitstreams For Fault Tolerance, David P. Montminy, Rusty O. Baldwin, Paul D. Williams
Relocatable Field Programmable Gate Array Bitstreams For Fault Tolerance, David P. Montminy, Rusty O. Baldwin, Paul D. Williams
AFIT Patents
A Field Programmable Gate Array (FPGA) circuit capable of operating through at least one fault. The FPGA circuit includes a configuration memory and an embedded microprocessor. The embedded microprocessor having access to the configuration memory, static modules, at least one relocatable module, and at least one spare module. The relocatable module being relocatable from a first target area to a second target area. The relocatable module being relocatable by manipulating a partial bitstream with the embedded microprocessor. The microprocessor calculating a plurality of bitstream changes, to relocate the at least one relocatable module using at least triple modular redundancy (TMR).
Hybrid Wafer Scale Microcircuit Integration -- [ 5008213 ], Edward S. Kolesar Jr.
Hybrid Wafer Scale Microcircuit Integration -- [ 5008213 ], Edward S. Kolesar Jr.
AFIT Patents
A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and hose wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment …
Hybrid Wafer Scale Microcircuit Integration -- [ 4989063 ], Edward S. Kolesar Jr.
Hybrid Wafer Scale Microcircuit Integration -- [ 4989063 ], Edward S. Kolesar Jr.
AFIT Patents
A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and host wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment …