Digital Circuits Commons^™

A Novel Design-For-Test Flow Using Librelane, Mohamed E. Gaber

Theses and Dissertations

Design-for-testing is a crucial element of application-specific integrated circuit design, yet, in the nascent open-source electronic design automation scene, the solutions for it are sorely limited. Design-for-test-enabled chips allow defects to be caught early on in the manufacturing process, avoiding incurring huge costs if hardware with defective chips is shipped to equipment manufacturers or, worse, end-users. Yet, the current open-source solutions rely on a brute-force utility that does not scale and negatively impacts the design by holding design-for-testing features as co-equal with the design’s regular operation, and a nominally layout-aware solution that does not holistically integrate into a larger flow. …

Open Source Asic Design Curriculum, Francisco Wilken

Master's Theses

The ever-growing importance of Application-Specific Integrated Circuits (ASICs) in a high-compute world necessitates that college graduates entering the workforce are well prepared to design them. This thesis details the design of novel ASIC curriculum, using open source tools to teach at the undergraduate level. By moving to a higher level of abstraction than classical transistor-focused coursework, chip design material can be made accessible earlier in an undergraduate degree. Additionally, open source tools provide a powerful, free, and portable platform for students to create their own designs, solving assignments focused on industry readiness. Finally, this thesis studies the results and challenges …

Cad Tools For Synthesis Of Sleep Convention Logic, Parviz Palangpour

Graduate Theses and Dissertations

This dissertation proposes an automated flow for the Sleep Convention Logic (SCL) asynchronous design style. The proposed flow synthesizes synchronous RTL into an SCL netlist. The flow utilizes commercial design tools, while supplementing missing functionality using custom tools. A method for determining the performance bottleneck in an SCL design is proposed. A constraint-driven method to increase the performance of linear SCL pipelines is proposed. Several enhancements to SCL are proposed, including techniques to reduce the number of registers and total sleep capacitance in an SCL design.

Full Custom Vlsi Design Of On-Line Stability Checkers, Chris Y. Lee

Master's Theses

A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.

A method for concurrent fault testing called On-line Stability Checking …