Open Access. Powered by Scholars. Published by Universities.®
- Discipline
-
- Electrical and Computer Engineering (9)
- Computer Sciences (5)
- Electrical and Electronics (5)
- Physical Sciences and Mathematics (5)
- Computer and Systems Architecture (4)
-
- Hardware Systems (4)
- VLSI and Circuits, Embedded and Hardware Systems (3)
- Aerospace Engineering (2)
- Digital Communications and Networking (2)
- Signal Processing (2)
- Artificial Intelligence and Robotics (1)
- Computational Engineering (1)
- Data Storage Systems (1)
- Electronic Devices and Semiconductor Manufacturing (1)
- Information Security (1)
- Other Aerospace Engineering (1)
- Other Electrical and Computer Engineering (1)
- Robotics (1)
- Space Vehicles (1)
- Systems Engineering and Multidisciplinary Design Optimization (1)
- Systems and Communications (1)
- Institution
- Keyword
-
- Logic circuits (3)
- Computer simulation (2)
- FPGA (2)
- Parallel processing (Electronic computers) (2)
- ASIC (1)
-
- Air pilots (1)
- Artificial intelligence (1)
- Boolean algebra (1)
- CNN (1)
- Chip design (1)
- Complementary metal oxide semiconductors (1)
- Computer-aided design (1)
- Coverage Analysis (1)
- Cyber attack (1)
- DEU (1)
- DFT (1)
- DPU (1)
- Data transmission systems (1)
- Deep Learning Accelerators (1)
- Design flows (1)
- Discrete-time systems (1)
- Edge computing (1)
- Electromagnetism (1)
- Error injection (1)
- Ethernet (Local area network system) (1)
- FCS (1)
- Fault Injection (1)
- Fault detection (1)
- Fault tolerance (1)
- Field programmable gate arrays (1)
Articles 1 - 22 of 22
Full-Text Articles in Digital Circuits
A Novel Design-For-Test Flow Using Librelane, Mohamed E. Gaber
A Novel Design-For-Test Flow Using Librelane, Mohamed E. Gaber
Theses and Dissertations
Design-for-testing is a crucial element of application-specific integrated circuit design, yet, in the nascent open-source electronic design automation scene, the solutions for it are sorely limited. Design-for-test-enabled chips allow defects to be caught early on in the manufacturing process, avoiding incurring huge costs if hardware with defective chips is shipped to equipment manufacturers or, worse, end-users. Yet, the current open-source solutions rely on a brute-force utility that does not scale and negatively impacts the design by holding design-for-testing features as co-equal with the design’s regular operation, and a nominally layout-aware solution that does not holistically integrate into a larger flow. …
Flexible Fault-Tolerant Multi-Die Fpga-Based Architectures For Varying Space Environments, Yosof Ali Seif El Din Ali Maklad
Flexible Fault-Tolerant Multi-Die Fpga-Based Architectures For Varying Space Environments, Yosof Ali Seif El Din Ali Maklad
Theses and Dissertations
It is well-known fact that spacecraft’s electronic components operate in an extreme harsh and varying space environments, beside changing orbit or passing through Van Allan Belts during orbital course results of radiation levels change. This thesis focuses on SRAM-based FPGA systems on-board of such spacecrafts, that are commonly utilized in space applications’ critical applications due to their capabilities and flexibility to reconfigure, since these systems are vulnerable to frequent negative impacts of ionizing radiation, thus inducing soft and hard errors leading to disastrous failures that could jeopardize the entire spacecraft. The soft errors’ effects are frequent yet can be mitigated, …
Design And Implementation Of Uvm-Based Verification Framework For Deep Learning Accelerators, Randa Ahmed Hussein Aboudeif
Design And Implementation Of Uvm-Based Verification Framework For Deep Learning Accelerators, Randa Ahmed Hussein Aboudeif
Theses and Dissertations
Recent advancements in deep learning (DL) have made hardware accelerators, known as deep learning accelerators (DLAs), a preferred solution for numerous high-performance computing (HPC) applications, including speech recognition, computer vision, and image classification. DLAs are composed of hundreds of parallel processing engines to speed up computations and can gain access to pre-trained networks from the cloud or through on-chip memory to implement the DNN inference process. DLA verification is becoming an important and challenging phase. The verification process is required to handle the complex DLA design. Moreover, the reliability of DLAs is critical for assessment as they are involved in …
Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad
Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad
Theses and Dissertations
Running computer vision algorithms requires complex devices with lots of computing power, these types of devices are not well suited for space deployment. The harsh radiation environment and limited power budgets have hindered the ability of running advanced computer vision algorithms in space. This problem makes running an on-orbit servicing detection algorithm very difficult. This work proposes using a low powered FPGA to accelerate the computer vision algorithms that enable satellite component feature extraction. This work uses AMD/Xilinx’s Zynq SoC and DPU IP to run model inference. Experiments in this work centered around improving model post processing by creating implementations …
Systematic Model-Based Design Assurance And Property-Based Fault Injection For Safety Critical Digital Systems, Athira Varma Jayakumar
Systematic Model-Based Design Assurance And Property-Based Fault Injection For Safety Critical Digital Systems, Athira Varma Jayakumar
Theses and Dissertations
With advances in sensing, wireless communications, computing, control, and automation technologies, we are witnessing the rapid uptake of Cyber-Physical Systems across many applications including connected vehicles, healthcare, energy, manufacturing, smart homes etc. Many of these applications are safety-critical in nature and they depend on the correct and safe execution of software and hardware that are intrinsically subject to faults. These faults can be design faults (Software Faults, Specification faults, etc.) or physically occurring faults (hardware failures, Single-event-upsets, etc.). Both types of faults must be addressed during the design and development of these critical systems. Several safety-critical industries have widely adopted …
Implementation Of A Hierarchical, Embedded, Cyber Attack Detection System For Spi Devices On Unmanned Aerial Systems, Jeremy J. Price
Implementation Of A Hierarchical, Embedded, Cyber Attack Detection System For Spi Devices On Unmanned Aerial Systems, Jeremy J. Price
Theses and Dissertations
Unmanned Aerial Systems (UAS) create security concerns as their roles expand in commercial, military, and consumer spaces. The need to secure these systems is recognized in the architecture for a Hierarchical, Embedded, Cyber Attack Detection (HECAD) system. HECAD passively monitors the communication between a flight controller and all its peripherals like sensors and actuators. It ensures the functionality of a UAS is within the set of defined behavior and reports all potential problems, whether the errors were caused by cyber attacks or other physical faults. A portion of the design for Serial Peripheral Interface (SPI) devices on board a flight …
Toward Biologically-Inspired Self-Healing, Resilient Architectures For Digital Instrumentation And Control Systems And Embedded Devices, Shawkat Sabah Khairullah
Toward Biologically-Inspired Self-Healing, Resilient Architectures For Digital Instrumentation And Control Systems And Embedded Devices, Shawkat Sabah Khairullah
Theses and Dissertations
Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes. One of the more essential concepts for achieving this goal is the notion of resilient and survivable digital I&C systems. In recent years, self-healing concepts based on biological physiology have received attention for the design of robust digital systems. However, many of these approaches have not been architected from the outset with safety in mind, nor have they been targeted for the automation community where a significant need exists. This dissertation presents a new self-healing digital …
Design Of An All-In-One Embedded Flight Control System, Joel D. Elmore
Design Of An All-In-One Embedded Flight Control System, Joel D. Elmore
Theses and Dissertations
This thesis describes an all-in-one flight control system (FCS) that was designed for unmanned aerial vehicles (UAVs). The project focuses on the embedded hardware aspect of a stand-alone system with low-cost and reliability in mind.
Characterization Of Metal-Insulator-Transition (Mit) Phase Change Materials (Pcm) For Reconfigurable Components, Circuits, And Systems, Brent L. Danner
Characterization Of Metal-Insulator-Transition (Mit) Phase Change Materials (Pcm) For Reconfigurable Components, Circuits, And Systems, Brent L. Danner
Theses and Dissertations
Many microelectromechanical systems (MEMS) use metal contact micro-switches as part of their reconfigurable device design. These devices utilize a mechanical component that can wear down and fail over time. Metal insulator transition (MIT) materials, also known as phase change materials (PCMs), exhibit a reversible transition that can be used to replace the mechanical component in reconfigurable devices. In the presence of a thermal or electric field stimuli, the PCMs will transition back and forth between a crystalline and amorphous state. During this transformation, the resistivity, reflectivity, and Young's modulus of the material drastically change. This research effort focuses on characterizing …
Critical Information Technology On Fpgas Through Unique Device Specific Keys, Miles E. Mcgee
Critical Information Technology On Fpgas Through Unique Device Specific Keys, Miles E. Mcgee
Theses and Dissertations
Field Programmable Gate Arrays (FPGAs) are being used for military and other sensitive applications, the threat of an adversary attacking these devices is an ever present danger. While having the ability to be reconfigured is helpful for development, it also poses the risk of its hardware design being cloned. Static random access memory (SRAM) FPGA's are the most common type of FPGA used in industry. Every time an SRAM-FPGA is powered up, its configuration must be downloaded. If an adversary is able to obtain that configuration, they can clone sensitive designs to other FPGAs. A technique that can be used …
Deterministic, Efficient Variation Of Circuit Components To Improve Resistance To Reverse Engineering, Daniel F. Koranek
Deterministic, Efficient Variation Of Circuit Components To Improve Resistance To Reverse Engineering, Daniel F. Koranek
Theses and Dissertations
This research proposes two alternative methods for generating semantically equivalent circuit variants which leave the circuit's internal structure pseudo-randomly determined. Component fusion deterministically selects subcircuits using a component identification algorithm and replaces them using a deterministic algorithm that generates canonical logic forms. Component encryption seeks to alter the semantics of individual circuit components using an encoding function, but preserves the overall circuit semantics by decoding signal values later in the circuit. Experiments were conducted to examine the performance of component fusion and component encryption against representative trials of subcircuit selection-and-replacement and Boundary Blurring, two previously defined methods for circuit obfuscation. …
Performance Evaluation Of A Field Programmable Gate Array-Based System For Detecting And Tracking Peer-To-Peer Protocols On A Gigabit Ethernet Network, Brennon D. Thomas
Performance Evaluation Of A Field Programmable Gate Array-Based System For Detecting And Tracking Peer-To-Peer Protocols On A Gigabit Ethernet Network, Brennon D. Thomas
Theses and Dissertations
Recent years have seen a massive increase in illegal, suspicious, and malicious traffic traversing government and military computer networks. Some examples include illegal file distribution and disclosure of sensitive information using the BitTorrent file sharing protocol, criminals and terrorists using Voice over Internet Protocol (VoIP) technologies to communicate, and foreign entities exfiltrating sensitive data from government, military, and Department of Defense contractor networks. As a result of these growing threats, the TRacking and Analysis for Peer-to-Peer (TRAPP) system was developed in 2008 to detect BitTorrent and VoIP traffic of interest. The TRAPP system, designed on a Xilinx Virtex-II Pro Field …
High Power Microwave (Hpm) And Ionizing Radiation Effects On Cmos Devices, Nicholas A. Estep
High Power Microwave (Hpm) And Ionizing Radiation Effects On Cmos Devices, Nicholas A. Estep
Theses and Dissertations
Integrated circuits (ICs) are inherently complicated and made worse by increasing transistor quantity and density. This trend potentially enhances concomitant effects of high energy radiation and local or impressed electromagnetic interference (EMI). The reduced margin for signal error may counter any gain in radiation hardness from smaller device dimensions. Isolated EMI and ionizing radiation studies on circuits have been conducted extensively over the past 30 years. However, little focus has been placed on the combined effects. To investigate the effect of combined EMI and ionizing radiation, two complementary metal oxide semiconductor (CMOS) inverter technologies (CD4069 and SN74AUC1G04) were analyzed for …
Chip To Chip Optical Interconnection Using Mems Mirrors, Tod V. Laurvick
Chip To Chip Optical Interconnection Using Mems Mirrors, Tod V. Laurvick
Theses and Dissertations
This experiment explores the use of MEMS mirrors to direct subsurface optical signals to another device and reception of those signals for use in chip to chip communications. Devices were built in PolyMUMPs to control horizontal and vertical beam direction and tilting in the outgoing signal and MEMS beam splitters for the incoming signal. Several elements of the outgoing beam path were successful and those which needed improvement indicate a high probability of success with limited trials needed and currently successful design elements could still be improved within the scope of PolyMUMPs. The incoming beam path elements were not successful …
Evaluation Of A Field Programmable Gate Array Circuit Reconfiguration System, Jason L. Ives
Evaluation Of A Field Programmable Gate Array Circuit Reconfiguration System, Jason L. Ives
Theses and Dissertations
This research implements a circuit reconfiguration system (CRS) to reconfigure a field programmable gate array (FPGA) in response to a faulty configurable logic block (CLB). It is assumed that the location of the fault is known and the CLB is moved according to one of four replacement methods: column left, column right, row up, and row down. Partial reconfiguration of the FPGA is done through the Joint Test Action Group (JTAG) port to produce the desired logic block movement. The time required to accomplish the reconfiguration is measured for each method in both clear and congested areas of the FPGA. …
Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec
Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec
Theses and Dissertations
The minimization of logic circuits has been an important area of research for more than a half century. The approaches taken in this field, however, have for the most part been ad hoc. Boolean techniques have been employed to manipulate formulas, but not to perform symbolic reasoning. Boolean equations are employed principally as icons; they are never solved. The first objective of this dissertation is to apply Boolean reasoning systematically and uniformly to the minimization problem. Boolean reasoning entails the reduction of systems of Boolean equations to a single equation; the single equation is an abstraction, independent of the form …
Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau
Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau
Theses and Dissertations
VHDL models are executed sequentially in current commercial simulators. As chip designs grow larger and more complex, simulations must run faster. One approach to increasing simulation speed is through parallel processors. This research transforms the behavioral and structural models created by Intermetrics' sequential VHDL simulator into models for parallel execution. The models are simulated on an Intel iPSC/2 hypercube with synchronization of the nodes being achieved by utilizing the Chandy Misra paradigm for discrete-event simulations. Three eight-bit adders, the ripple carry, the carry save, and the carry-lookahead, are each run through the parallel simulator. Simulation time is cut in at …
Electrically Erasable Programmable Integrated Circuits For Replacement Of Obsolete Ttl Logic, Joseph V. Breen
Electrically Erasable Programmable Integrated Circuits For Replacement Of Obsolete Ttl Logic, Joseph V. Breen
Theses and Dissertations
Two microcircuits with electrically erasable programmable logic arrays, which use Fowler-Nordheim (F-N) tunneling for both programming and erasing, were designed to demonstrate the use of programmable logic for obsolete TTL logic replacement. Each microcircuit was fabricated in the Orbit 2-micron double-poly low noise analog CMOS process through MOSIS. Software to generate VHDL structural models from a pin list was developed and the logic of both designs was verified by simulation using the Zycad VHDL simulator. The first microcircuit included a simple programmable logic circuit and test cells that allowed measurement of the programming characteristics of the floating gate transistors. Test …
A Prolog-Based System For Hardware Verification, Kevin L. Sparks
A Prolog-Based System For Hardware Verification, Kevin L. Sparks
Theses and Dissertations
With the expanding number of components provided on a single digital chip, verification of digital designs is becoming a major problem. The more circuits one places on a single chip, the greater the number of input/output combinations which need to be checked. A paper by Barrow in 1984 discusses a Prolog-based hierarchical formal verification system which he calls VERIFY. Barrow provided a lot of information on what VERIFY can and cannot do, and on projected enhancements. He does not, however, mention how VERIFY actually performs the task of formal verification. This thesis will provide a description of one possible implementation …
Optimal Iterative Task Scheduling For Parallel Simulations, Joann M. Sartor
Optimal Iterative Task Scheduling For Parallel Simulations, Joann M. Sartor
Theses and Dissertations
The ultimate purpose of this research is to reduce the time needed for execution of parallel computer simulations. In particular, the impact of task assignment strategies is determined for parallel VHDL circuit simulations. The classical scheduling problem, which assigns n precedence-constrained tasks to m processors is NP-complete in all but the simplest cases. The problem of assigning simulation tasks is further complicated by the iterative nature of computer simulations: each task is required to execute multiple times as the simulation executes. This investigation develops a polynomial-time algorithm (the level strategy) which provides optimal assignment for iterative systems with specific constraints. …
Recursive Optimization Of Digital Circuits, John Knutson
Recursive Optimization Of Digital Circuits, John Knutson
Theses and Dissertations
The goal of this thesis is twofold: first, to identify the advantages and disadvantages of existing optimization systems and second, to develop an optimization system that uses Boolean principles to generate a recursive realization of combinational logic. Current multi-level optimization systems fall into two categories: local optimization which removes redundancy by pattern matching on a local scale and global optimization which works with the equations that specify a circuit rather than with the circuit implementation itself. While global systems are very flexible and can produce near-optimal solutions, they are inherently complex. This research effort demonstrates that an effective global optimization …
Specification And Equivalence Verification Of Sequential Circuits Via Vhdl, Richard L. Miller
Specification And Equivalence Verification Of Sequential Circuits Via Vhdl, Richard L. Miller
Theses and Dissertations
This research presents a merger of the specification and design capabilities of the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) with a known verification method (UC Berkeley's verify software) in order to solve the design and verification problem of sequential circuits. The fruits of this research are a behavioral VHDL model for sequential circuit specification, a structural VHDL model for sequential circuit design, and a method for comparing two circuits described using these VHDL models in order to demonstrate circuit equivalence. The behavioral and structural VHDL models were developed and tested within the Intermetric's VHDL software support …