Digital Circuits Commons^™

Reproducing And Evaluating Charger Surfing: Robustness Of Smartphone Charging-Line Side-Channels, Colby M. Watts

Master's Theses

Smartphones are frequently connected to external, untrusted charging hardware, creating opportunities for side-channel attacks that do not require malware or direct access to device data. Charger Surfing, a recently proposed charging-line power analysis side-channel attack, reported high accuracy in inferring touchscreen input from voltage measurements collected from a smartphone’s charging cable; however, the reproducibility and robustness of these results under different conditions remain unclear. This thesis presents an independent replication and evaluation of Charger Surfing, including the development of an end-to-end data collection pipeline consisting of a modified charging cable, oscilloscope-based recordings, custom Android app, automated trace processing, and convolutional …

Improving Human Visual Search: Enhancing Lung Cancer Nodule Detection In Medical Images, Christopher Khajira

Masters Theses

Human visual search involves the identification of relevant signals within information-rich environments, which is a fundamental problem in visual perception. While detection accuracy and response time are commonly used to evaluate performance in visual search, these measures do not reveal the underlying cognitive and computational structure that produces observable behavior. A key challenge lies in distinguishing between competing processing architectures, particularly in complex visual domains where different models can produce similar behavioral outcomes. This study addresses this challenge by developing a computational experimental framework for analyzing visual search behavior using System Factorial Technology (SFT). The experimental framework integrates naturalistic medical …

Exploration Of Real-Time Power Electronic Simulation On Amd Npu, Shouyu Du

All Theses

The rapid electrification of the automotive and data center sectors has created a critical demand for high-fidelity, real-time simulation of complex power electronic systems. While Hardware- in-the-Loop (HIL) simulation on Field-Programmable Gate Arrays (FPGAs) is the current industry standard, it presents significant challenges regarding development complexity and memory limita- tions. This dissertation investigates the feasibility of utilizing Neural Processing Units (NPUs)— specifically the AMD AI Engine (AIE) XDNA2 architecture—as a novel platform for real-time, deterministic circuit simulation. This study establishes a comprehensive automated modeling framework based on graph theory and Massarini’s method to derive linear state-space representations for arbitrary circuit …

Design And Verification Of The Multi-Slit Solar Explorer Camera Field Programmable Gate Arrays, Jordan M. Johnson

All Graduate Reports and Creative Projects, Fall 2023 to Present

The Multi-Slit Solar Explorer, or MUSE, is a NASA mission that will take images of the Sun to study solar flares and the solar corona. The mission will provide insight into the mechanisms behind space weather. The mission consists of two cameras: the Spectrograph (SG), and the Context Imager (CI). The Utah State University Space Dynamics Laboratory is providing both cameras for the mission.

This report describes a part of the design and verification process for a central component on these cameras known as the Field Programmable Gate Arrays (FPGAs). These FPGAs are programmed to acquire, handle, and send images …

Ai-Scm Cmm: A Capability Maturity Model For Artificial Intelligence Integration In Supply Chain Management, Lordt Becklines, Omar F. El-Gayar, Patti Brooks, Insu Park

Annual Research Symposium

Artificial intelligence is increasingly deployed in supply chain management, yet many organizations struggle to align adoption efforts with process readiness, data quality, governance, and workforce capabilities, and they still lack validated supply chain specific roadmap for assessing readiness, sequencing investments, and reducing implementation risk. This study develops and evaluates a Capability Maturity Model for Artificial Intelligence Integration in Supply Chain Management to address that gap. Using a design science research approach, the study synthesizes prior literature and practitioner knowledge to define maturity dimensions, capability indicators, and staged progression levels for AI integration in supply chain contexts. The artifact and assessment …

A Capability Maturity Model For Artificial Intelligence Integration In Supply Chain Management, Lordt Becklines

Dissertations

Artificial Intelligence (AI) is transforming Supply Chain Management (SCM), yet many organizations struggle to assess their readiness for AI adoption and to understand how AI capabilities develop across maturity stages. This dissertation addresses this gap by developing a Capability Maturity Model (CMM) for AI integration in SCM, grounded in Organizational Information Processing Theory (OIPT), the Resource-Based View, and related capability frameworks. The model provides a structured approach for evaluating an organization's information-processing requirements, resource configurations, and alignment needed for effective AI-enabled supply chain operations.

Using a design science research approach, the AI-SCM CMM and its associated assessment instrument were derived …

True-Bsg: A True Random Bit-Stream Generator For Fast And Efficient Stochastic Computing, Mehran Shoushtari Moghadam, M. Hassan Najafi

Faculty Scholarship

Stochastic computing (SC) leverages random bitstreams to perform arithmetic operations, offering ultra-lowcost, fault-tolerant, and highly parallelizable computations. The quality of these bit-streams is crucial for the accuracy and reliability of SC. This paper introduces TRUE-BSG, a novel true random bit-stream generator designed for fast and energyefficient SC. Unlike state-of-the-art (SoTA) pseudo-random and quasi-random bit-stream generators, TRUE-BSG utilizes a highquality true random number generator (TRNG), capable of producing random bits at a rate of 1 Gigabit per second. Our TRNG ensures high entropy and minimal correlation. TRUE-BSG shows comparable accuracy to software-based generators and better energy efficiency than SoTA bit-stream generators, …

Breaking New Ground: Division Directly In Memory, M. Hassan Najafi, Mehran Shoushtari Moghadam

Faculty Scholarship

In-memory computing (IMC) has emerged as a promising paradigm for overcoming the limitations of traditional von Neumann architectures by reducing data movement and enhancing computational efficiency. Despite significant advancements in this area, implementing complex arithmetic operations, such as division, directly within memory has remained an elusive challenge. This paper introduces a pioneering technique for performing division operations directly in memory, representing the first successful integration of such functionality into the IMC framework. Our approach leverages an innovative circuit based on an unconventional model of computing–stochastic computing (SC). Our technique extends the computational capabilities of IMC systems and paves the way …

Design Considerations Of A Gpu, Nicholas M. Devilliers

Electrical Engineering and Computer Science Undergraduate Honors Theses

With the current era of AI technology, the era of single instruction multiple data has become an increasingly viable solution to accelerate training. The problem is that while software to use GPUs and other hardware accelerators, designing GPUs and ASIC devices has become increasingly more expensive and there aren’t great examples of generic GPUs that anyone can use and modify. In this thesis, there are four design considerations that will be discussed and how they affect the result of a generic GPU. The four considerations that were talked about in the thesis are, word width, arithmetic type, number of stages, …

Design And Implementation Of Uvm-Based Verification Framework For Deep Learning Accelerators, Randa Ahmed Hussein Aboudeif

Theses and Dissertations

Recent advancements in deep learning (DL) have made hardware accelerators, known as deep learning accelerators (DLAs), a preferred solution for numerous high-performance computing (HPC) applications, including speech recognition, computer vision, and image classification. DLAs are composed of hundreds of parallel processing engines to speed up computations and can gain access to pre-trained networks from the cloud or through on-chip memory to implement the DNN inference process. DLA verification is becoming an important and challenging phase. The verification process is required to handle the complex DLA design. Moreover, the reliability of DLAs is critical for assessment as they are involved in …

Exploring Smart Thermostat, Don P. Dang

2024 Fall Honors Capstone Projects - Archive

This study examines the security, privacy, and compatibility challenges associated with smart thermostats in smart home systems. Smart thermostats, as part of the growing Internet of Things (IoT) ecosystem, face vulnerabilities such as unauthorized access, data breaches, and inconsistent security protocols. Using a mixed-methods approach, this research evaluates encryption techniques, communication protocols (Zigbee, Z-Wave, Wi Fi), and user behaviors that impact system security and efficiency. Key findings indicate that 35% of users are concerned about hacking risks, while 25% express data privacy concerns. Many users lack awareness of security measures, such as firmware updates and password management, which increases vulnerabilities. …

Trisc: Low-Cost Design Of Trigonometric Functions With Quasi Stochastic Computing, Mehran Shoushtari Moghadam, M. Hassan Najafi

Faculty Scholarship

Low-cost and hardware-efficient design of trigonometric functions is challenging. Stochastic computing (SC), an emerging computing model processing random bit-streams, offers promising solutions for this problem. The existing implementations, however, often overlook the importance of the data converters necessary to generate the needed bit-streams. While recent advancements in SC bit-stream generators focus on basic arithmetic operations such as multiplication and addition, energy-efficient SC design of non-linear functions demands attention to both the computation circuit and the bit-stream generator. This work introduces TriSC, a novel approach for SC-based design of trigonometric functions enjoying state-of-the-art (SOTA) quasi-random bit-streams. Unlike SOTA SC designs of …

Prototyping Interactive Tactile Digital Logic Simulations: A Hybrid Approach, Logan Bateman

MS in Computer Science Project Reports

Tactile exhibits are common in museums and on the walls of university halls. However, few (if any) tools exist for creating tactile exhibits for teaching digital logic or computing concepts. This project implemented a framework for creating tactile digital logic simulation exhibits, with a focus on rapid prototyping and distributed architecture. Prototyping allows for fast iteration, with the ability to simulate unlimited hardware components such as buttons, light emitting diodes (LEDs), and other input or output devices. Through the abstraction of implementations and a distributed communication protocol, switching to real hardware is seamless and works in tandem with simulated hardware. …

All You Need Is Unary: End-To-End Bit-Stream Processing In Hyperdimensional Computing, Mehran Shoushtari Moghadam, M. Hassan Najafi

Faculty Scholarship

Hyperdimensional Computing (HDC) is a brain-inspired computing paradigm introduced to achieve energy efficiency with a lightweight and single-pass training model. Hypervectors (HVs) at the heart of the HDC systems play a fundamental role in elevating the accuracy and obtaining the desired performance. Image-based HV encoding requires two types of HVs: Position and Level HVs. State-of-the-art approaches utilize pseudo-random methods for generating these HVs, which might degrade system performance and cause higher power consumption due to poor randomness in HV generation. These conventional methods require iteratively calculating orthogonal Positional HVs for acceptable accuracy. This work proposes a fast, ultra-lightweight, and high-quality …

Uhd: Unary Processing For Lightweight And Dynamic Hyperdimensional Computing, Mehran Shoushtari Moghadam, M. Hassan Najafi

Faculty Scholarship

Hyperdimensional computing (HDC) is a novel computational paradigm that operates on long-dimensional vectors known as hypervectors. The hypervectors are constructed as long bit-streams and form the basic building blocks of HDC systems. In HDC, hypervectors are generated from scalar values without considering bit significance. HDC is efficient and robust for various data processing applications, especially computer vision tasks. To construct HDC models for vision applications, the current state-of-the-art practice utilizes two parameters for data encoding: pixel intensity and pixel position. However, the intensity and position information embedded in high-dimensional vectors are generally not generated dynamically in the HDC models. Consequently, …

Building A Wireless Electronic Control Unit For An Electric Vehicle, Hector S. Sosa

2024 Spring Honors Capstone Projects - Archive

Modern vehicles have a variety of features such remote start systems, advance drive assist systems, smart suspension systems, and a feature rich infotainment system. With all this technology in the car, there exists a complex network of computers working together in conjunction to deliver the modern driving experience that many people have today. To be competitive in the market, auto manufacturers are tasked to add additional features to vehicles by adding additional or modifying electronic control units (ECUs). In this study, an ECU will be designed for a mock electric vehicle which contains an already established network of ECU’s. The …

A Novel Processor Architecture Implementing The Stacked Error Diffusion Algorithm And Its Zynq-Based Realization, Qishi Hu

Theses and Dissertations--Electrical and Computer Engineering

Digital halftoning reproduces continuous-tone images using patterns of black and white dots, while multitoning extends this concept by incorporating inks with intermediate intensities. These techniques are extensively utilized in the printing industry to accommodate the limited range of inks available in printers. Stacked error diffusion is a high-quality multitoning algorithm that adheres to the blue-noise dithering standard. This thesis research studies the potential parallelism inherent in the algorithm and introduces the design of a novel processor architecture optimized for efficient execution. The architecture is realized on an FPGA development board featuring a Zynq SoC. Additionally, the hardware prototype can also …

Gen-Acceleration: Pioneering Work For Hardware Accelerator Generation Using Large Language Models, Durga Lakshmi Venkata Deepak Vungarala

Theses

Optimizing computational power is critical in the age of data-intensive applications and Artificial Intelligence (AI)/Machine Learning (ML). While facing challenging bottlenecks, conventional Von-Neumann architecture with implementing such huge tasks looks seemingly impossible. Hardware Accelerators are critical in efficiently deploying these technologies and have been vastly explored in edge devices. This study explores a state-of-the-art hardware accelerator; Gemmini is studied; we leveraged the open-sourced tool. Furthermore, we developed a Hardware Accelerator in the study we compared with the Non-Von-Neumann architecture. Gemmini is renowned for efficient matrix multiplication, but configuring it for specific tasks requires manual effort and expertise. We propose implementing …

Low-Power, Event-Driven System On A Chip For Charge Pulse Processing Applications, Joseph A. Schmitz

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

This dissertation presents an electronic architecture and methodology capable of processing charge pulses generated by a range of sensors, including radiation detectors and tactile synthetic skin. These sensors output a charge signal proportional to the input stimulus, which is processed electronically in both the analog and digital domains. The presented work implements this functionality using an event-driven methodology, which greatly reduces power consumption compared to standard implementations. This enables new application areas that require a long operating time or compact physical dimensions, which would not otherwise be possible. The architecture is designed, fabricated, and tested in the aforementioned applications to …

Remote Side-Channel Disassembly On Field-Programmable Gate Arrays, Brandon R. Baggett

Graduate Theses and Dissertations (2019 - present)

Over the last two decades, side-channel vulnerabilities have shown to be a major threat to embedded devices. Most side-channel research has developed our understanding of the vulnerabilities to cryptographic devices due to their implementation and how we can protect them. However, side-channel leakage can yield useful information about many other processes that run on the device. One promising area that has received little attention is the side-channel leakage due to the execution of assembly instructions. There has been some work in this area that has demonstrated the idea’s potential, but so far, this research has assumed the adversary has physical …

Digital Simulations Of Memristors Towards Integration With Reconfigurable Computing, Ivris Raymond

Computer Science and Computer Engineering Undergraduate Honors Theses

The end of Moore’s Law has been predicted for decades. Demand for increased parallel computational performance has been increased by improvements in machine learning. This past decade has demonstrated the ever-increasing creativity and effort necessary to extract scaling improvements in CMOS fabrication processes. However, CMOS scaling is nearing its fundamental physical limits. A viable path for increasing performance is to break the von Neumann bottleneck. In-memory computing using emerging memory technologies (e.g. ReRam, STT, MRAM) offers a potential path beyond the end of Moore’s Law. However, there is currently very little support from industry tools for designers wishing to incorporate …

Chatgpt As Metamorphosis Designer For The Future Of Artificial Intelligence (Ai): A Conceptual Investigation, Amarjit Kumar Singh (Library Assistant), Dr. Pankaj Mathur (Deputy Librarian)

Library Philosophy and Practice (e-journal)

Abstract

Purpose: The purpose of this research paper is to explore ChatGPT’s potential as an innovative designer tool for the future development of artificial intelligence. Specifically, this conceptual investigation aims to analyze ChatGPT’s capabilities as a tool for designing and developing near about human intelligent systems for futuristic used and developed in the field of Artificial Intelligence (AI). Also with the helps of this paper, researchers are analyzed the strengths and weaknesses of ChatGPT as a tool, and identify possible areas for improvement in its development and implementation. This investigation focused on the various features and functions of ChatGPT that …

Towards Multipronged On-Chip Memory And Data Protection From Verification To Design And Test, Senwen Kan, Jennifer Dworak

Computer Science and Engineering Theses and Dissertations

Modern System on Chips (SoCs) generally include embedded memories, and these memories may be vulnerable to malicious attacks such as hardware trojan horses (HTHs), test access port exploitation, and malicious software. This dissertation contributes verification as well as design obfuscation solutions aimed at design level detection of memory HTH circuits as well as obfuscation to prevent HTH triggering for embedded memory during functional operation. For malicious attack vectors stemming from test/debug interfaces, this dissertation presents novel solutions that enhance design verification and securitization of an IJTAG based test access interface. Such solutions can enhance SoC protection by preventing memory test …

Applying Hls To Fpga Data Preprocessing In The Advanced Particle-Astrophysics Telescope, Meagan Konst

McKelvey School of Engineering Graduate Student Theses & Dissertations

The Advanced Particle-astrophysics Telescope (APT) and its preliminary iteration the Antarctic Demonstrator for APT (ADAPT) are highly collaborative projects that seek to capture gamma-ray emissions. Along with dark matter and ultra-heavy cosmic ray nuclei measurements, APT will provide sub-degree localization and polarization measurements for gamma-ray transients. This will allow for devices on Earth to point to the direction from which the gamma-ray transients originated in order to collect additional data. The data collection process is as follows. A scintillation occurs and is detected by the wavelength-shifting fibers. This signal is then read by an ASIC and stored in an ADC …

Live Access Control Policy Error Detection Through Hardware, Bryce Mendenhall

Graduate Theses and Dissertations

Access Control (AC) is a widely used security measure designed to protect resources and infrastructure in an information system. The integrity of the AC policy is crucial to the protection of the system. Errors within an AC policy may cause many vulnerabilities such as information leaks, information loss, and malicious activities. Thus, such errors must be detected and promptly fixed. However, current AC error detection models do not allow for real-time error detection, nor do they provide the source of errors. This thesis presents a live error detection model called LogicDetect which utilizes emulated Boolean digital logic circuits to provide …

Development Of A Reference Design For Intrusion Detection Using Neural Networks For A Smart Inverter, Ammar Mohammad Khan

Graduate Theses and Dissertations

The purpose of this thesis is to develop a reference design for a base level implementation of an intrusion detection module using artificial neural networks that is deployed onto an inverter and runs on live data for cybersecurity purposes, leveraging the latest deep learning algorithms and tools. Cybersecurity in the smart grid industry focuses on maintaining optimal standards of security in the system and a key component of this is being able to detect cyberattacks. Although researchers and engineers aim to design such devices with embedded security, attacks can and do still occur. The foundation for eventually mitigating these attacks …

Low-Power And Reconfigurable Asynchronous Asic Design Implementing Recurrent Neural Networks, Spencer Nelson

Graduate Theses and Dissertations

Artificial intelligence (AI) has experienced a tremendous surge in recent years, resulting in high demand for a wide array of implementations of algorithms in the field. With the rise of Internet-of-Things devices, the need for artificial intelligence algorithms implemented in hardware with tight design restrictions has become even more prevalent. In terms of low power and area, ASIC implementations have the best case. However, these implementations suffer from high non-recurring engineering costs, long time-to-market, and a complete lack of flexibility, which significantly hurts their appeal in an environment where time-to-market is so critical. The time-to-market gap can be shortened through …

Annual Report 2020-2021, Depaul University College Of Computing And Digital Media

CDM Annual Reports

LETTER FROM THE DEAN

As I write this letter during the beginning of the 2021–22 academic year, we have started to welcome the majority of our students to campus— many for the very first time, and some for the first time in a year and a half. It has been wonderful to be together, in-person, again. Four quarters of learning and working remotely was challenging, to be sure, but I have been consistently amazed by the resilience, innovation, and hard work of our students, faculty, and staff, even in the most difficult of circumstances. This annual report, covering the 2020–21 …

Light Loaded Automated Guided Vehicle, Marcus Radtka, Nazar Paramashchuk, Lawrence Shevock

Williams Honors College, Honors Research Projects

The objective of the locomotion system was to design and implement the mechanical, electrical, and software related functions to ensure the LLAGV had the capability of maneuvering its surroundings. The LLAGV’s motors were represented in an open loop transfer function to utilize RPM feedback and a compensator when needed. The modeled compensator helped control the LLAGV’s speed and acceleration, enabling further control of the LLAGV. The internal circuitry has the means to properly distributed power to all components and allowed the user to control the LLAGV to their desire. The application software within the LLAGV locomotion system (LLAGV-LS) had consideration …

Models And Methods Of Designing Human-Machine Interaction-Oriented Interfaces, Ozod Radjabov, Shakhrillo Bobokulov, Behruz Boboqulov, Hojiyev Sunatullo

Bulletin of TUIT: Management and Communication Technologies

Formalization approaches of user interface design (UID) in conjunction with model driven techniques aim to improve the usability in terms of conformity to standards or style guides and to leverage code generation of interactive software systems, so that various UI platforms for web, desktop or mobile Applications are supported. Because large parts of the UI are described platform independent instead of platform dependent implementations, re-usability of the UI concept is also improved. However, UI formalization requires the usage of a formal UI description language and a higher level of abstractness compared to concrete UI code. These languages need to be …