Digital Circuits Commons^™

A Study On Quantization And Hardware Cost Tradeoffs In A 5g Nr Ldpc Decoder On Fpga, Giancarlo Acosta

Master's Theses

The fixed-point implementation of a 5G New Radio LDPC decoder forces a tradeoff between precision and hardware cost, governed by the variable node word length W_L, the check node message width W_R, and the normalized min-sum correction factor α. This thesis characterizes how these three parameters affect both error correction performance and FPGA resource utilization for an LDPC decoder on an established LDPC decoder architecture. A bit-accurate MATLAB core model records bit error rate (BER) and frame error rate (FER) while a verified HDL Coder model generates synthesizable VHDL for Vivado synthesis, and both are swept …

Reproducing And Evaluating Charger Surfing: Robustness Of Smartphone Charging-Line Side-Channels, Colby M. Watts

Master's Theses

Smartphones are frequently connected to external, untrusted charging hardware, creating opportunities for side-channel attacks that do not require malware or direct access to device data. Charger Surfing, a recently proposed charging-line power analysis side-channel attack, reported high accuracy in inferring touchscreen input from voltage measurements collected from a smartphone’s charging cable; however, the reproducibility and robustness of these results under different conditions remain unclear. This thesis presents an independent replication and evaluation of Charger Surfing, including the development of an end-to-end data collection pipeline consisting of a modified charging cable, oscilloscope-based recordings, custom Android app, automated trace processing, and convolutional …

Open Source Asic Design Curriculum, Francisco Wilken

Master's Theses

The ever-growing importance of Application-Specific Integrated Circuits (ASICs) in a high-compute world necessitates that college graduates entering the workforce are well prepared to design them. This thesis details the design of novel ASIC curriculum, using open source tools to teach at the undergraduate level. By moving to a higher level of abstraction than classical transistor-focused coursework, chip design material can be made accessible earlier in an undergraduate degree. Additionally, open source tools provide a powerful, free, and portable platform for students to create their own designs, solving assignments focused on industry readiness. Finally, this thesis studies the results and challenges …

Mos Current Mode Logic (Mcml) Analysis For Quiet Digital Circuitry And Creation Of A Standard Cell Library For Reducing The Development Time Of Mixed Signal Chips, David Marusiak

Master's Theses

Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with …

Digital Control Board For Phased Array Antenna Beam Steering In Adaptive Communication Applications, Mayur Bansal

Master's Theses

The application of adaptive communication techniques for mobile communications has attracted considerable interest in the last decade. One example of these techniques is spatial filtering through planar antenna array beam forming.

This thesis describes the development of a digital system that adaptively controls a phased array antenna. The radiating structure of the phased antenna array is tetrahedral-shaped and contains four antenna elements on each of its three faces. The overall system comprises of a digital control board with an external computer interface, an RF control board, and the phased antenna array. The RF controls the main lobe direction on the …

Full Custom Vlsi Design Of On-Line Stability Checkers, Chris Y. Lee

Master's Theses

A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.

A method for concurrent fault testing called On-line Stability Checking …

Asynchronous Mips Processors: Educational Simulations, Robert L. Webb

Master's Theses

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …