VLSI and Circuits, Embedded and Hardware Systems Commons^™

Protecting Return Address Integrity For Risc-V Via Pointer Authentication, Yuhe Zhao

Masters Theses

Embedded systems based on lightweight microprocessors are becoming more prevalent in various applications. However, the security of them remains a significant challenge due to the limited resources and exposure to external threats. Especially, some of these devices store sensitive data and control critical devices, making them high-value targets for attackers. Software security is particularly important because attackers can easily access these devices on the internet and obtain control of them by injecting malware.

Return address (RA) hijacking is a common software attack technique used to compromise control flow integrity (CFI) by manipulating memory, such as return-to-libc attacks. Several methods have …

Incorporating Machine Learning With Satellite Data To Support Critical Infrastructure Measurement And Sustainable Development, Aggrey Muhebwa

Doctoral Dissertations

Under the umbrella concept of Artificial Intelligence (AI) for good, recent advances in machine learning and large-scale data analysis have opened new opportunities to solve humanity’s most pressing challenges. Improvements in computation complexity and advances in AI (e.g., Vision Transformers) have led to faster and more effective techniques for extracting high-dimensional patterns from large-scale heterogeneous datasets (big data). Further, as satellite data become increasingly available at varying temporal-spatial resolutions, AI tools are helping us to better understand the underlying causes of environmental and socioeconomic changes at an unprecedented scale, ushering in an era of data-driven decision-making to support sustainable and …

A Sindy Hardware Accelerator For Efficient System Identification On Edge Devices, Michael Sean Gallagher

Master's Theses

The SINDy (Sparse Identification of Non-linear Dynamics) algorithm is a method of turning a set of data representing non-linear dynamics into a much smaller set of equations comprised of non-linear functions summed together. This provides a human readable system model the represents the dynamic system analyzed. The SINDy algorithm is important for a variety of applications, including high precision industrial and robotic applications. A Hardware Accelerator was designed to decrease the time spent doing calculations. This thesis proposes an efficient hardware accelerator approach for a broad range of applications that use SINDy and similar system identification algorithms. The accelerator is …

Reinventing Integrated Photonic Devices And Circuits For High Performance Communication And Computing Applications, Venkata Sai Praneeth Karempudi

Theses and Dissertations--Electrical and Computer Engineering

The long-standing technological pillars for computing systems evolution, namely Moore's law and Von Neumann architecture, are breaking down under the pressure of meeting the capacity and energy efficiency demands of computing and communication architectures that are designed to process modern data-centric applications related to Artificial Intelligence (AI), Big Data, and Internet-of-Things (IoT). In response, both industry and academia have turned to 'more-than-Moore' technologies for realizing hardware architectures for communication and computing. Fortunately, Silicon Photonics (SiPh) has emerged as one highly promising ‘more-than-Moore’ technology. Recent progress has enabled SiPh-based interconnects to outperform traditional electrical interconnects, offering advantages like high bandwidth density, …

Gen-Acceleration: Pioneering Work For Hardware Accelerator Generation Using Large Language Models, Durga Lakshmi Venkata Deepak Vungarala

Theses

Optimizing computational power is critical in the age of data-intensive applications and Artificial Intelligence (AI)/Machine Learning (ML). While facing challenging bottlenecks, conventional Von-Neumann architecture with implementing such huge tasks looks seemingly impossible. Hardware Accelerators are critical in efficiently deploying these technologies and have been vastly explored in edge devices. This study explores a state-of-the-art hardware accelerator; Gemmini is studied; we leveraged the open-sourced tool. Furthermore, we developed a Hardware Accelerator in the study we compared with the Non-Von-Neumann architecture. Gemmini is renowned for efficient matrix multiplication, but configuring it for specific tasks requires manual effort and expertise. We propose implementing …

Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad

Theses and Dissertations

Running computer vision algorithms requires complex devices with lots of computing power, these types of devices are not well suited for space deployment. The harsh radiation environment and limited power budgets have hindered the ability of running advanced computer vision algorithms in space. This problem makes running an on-orbit servicing detection algorithm very difficult. This work proposes using a low powered FPGA to accelerate the computer vision algorithms that enable satellite component feature extraction. This work uses AMD/Xilinx’s Zynq SoC and DPU IP to run model inference. Experiments in this work centered around improving model post processing by creating implementations …

A Case Study In Cmos Design Scaling For Analog Applications: The Ringamp Ldo, Steven Corum

Masters Theses

As CMOS process nodes scale to smaller feature sizes, process optimizations are made to achieve improvements in digital circuit performance, such as increasing speed and memory, while decreasing power consumption. Unfortunately for analog design, these optimizations usually come at the expense of poorer transistor performance, such as reduced small signal output resistance and increased channel length modulation. The ring amplifier has been proposed as a digital solution to the analog scaling problem, by configuring digital inverters to function as analog amplifiers through deadzone biasing. As digital inverters naturally scale, the ring amplifier is a promising area of exploration for analog …

Low-Power, Event-Driven System On A Chip For Charge Pulse Processing Applications, Joseph A. Schmitz

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

This dissertation presents an electronic architecture and methodology capable of processing charge pulses generated by a range of sensors, including radiation detectors and tactile synthetic skin. These sensors output a charge signal proportional to the input stimulus, which is processed electronically in both the analog and digital domains. The presented work implements this functionality using an event-driven methodology, which greatly reduces power consumption compared to standard implementations. This enables new application areas that require a long operating time or compact physical dimensions, which would not otherwise be possible. The architecture is designed, fabricated, and tested in the aforementioned applications to …

Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya

Theses and Dissertations

High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a …

A Moving Target Architecture As A Side-Channel Countermeasure, Rachel M. Cazzola

Electrical and Computer Engineering ETDs

We investigate a novel side-channel attack countermeasure called Side-channel Power analysis Resistance for Encryption Algorithms using Dynamic partial reconfiguration (SPREAD). The countermeasure leverages a strategy that is best characterized as a moving target architecture. Modern field-programmable gate array (FPGA) architectures provide support for dynamic partial reconfiguration (DPR), a feature that allows real-time reconfiguration of portions of the programmable logic (PL) while the FPGA continues to carry out computing tasks. Using the Advanced Encryption Standard (AES), the proposed moving target architecture leverages DPR to change the implementation characteristics of the substitution boxes (SBOX) in real time. We present experimental hardware results …

Creating An Automatic Lowering Function For Quarter-Scale Tractor Pulling Sled, Sam Wilkins

Honors Theses

As the agricultural industry works to continuously integrate innovative technology and improve production efficiency, improved on-board data acquisition and transmission will be necessary for all agricultural machines. To make this a reality, the utilization of controller area network (CAN) technology will be crucial. Therefore, it is important for all agricultural engineers to have foundational knowledge of CAN bus systems and the standards that govern their use in industry. The UNL quarter-scale tractor team regularly utilizes CAN buses on their tractors and testing equipment. One such testing machine is the team’s pulling sled, which uses CAN messages to transport important information …

Fingerprinting For Chiplet Architectures Using Power Distribution Network Transients, Matthew G. Burke

Masters Theses

Chiplets have become an increasingly popular technology for extending Moore's Law and improving the reliability of integrated circuits. They do this by placing several small, interacting chips on an interposer rather than the traditional, single chip used for a device. Like any other type of integrated circuit, chiplets are in need of a physical layer of security to defend against hardware Trojans, counterfeiting, probing, and other methods of tampering and physical attacks.

Power distribution networks are ubiquitous across chiplet and monolithic ICs, and are essential to the function of the device. Thus, we propose a method of fingerprinting transient signals …

Sel4 On Risc-V - Developing High Assurance Platforms With Modular Open-Source Architectures, Michael A. Doran Jr

Masters Theses

Virtualization is now becoming an industry standard for modern embedded systems. Modern embedded systems can now support multiple applications on a single hardware platform while meeting power and cost requirements. Virtualization on an embedded system is achieved through the design of the hardware-software interface. Instruction set architecture, ISA, defines the hardware-software interface for an embedded system. At the hardware level the ISA, provides extensions to support virtualization.

In addition to an ISA that supports hypervisor extensions it is equally important to provide a hypervisor completely capable of exploiting the benefits of virtualization for securing modern embedded systems. Currently there does …

A Portable, Low Power Radiation Detection And Identification System For High Count Rate, Long Term Monitoring, Samuel J. Murray

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

This dissertation presents the design of a novel radiation detection and identification system that can operate continuously over a period of 8 days while detecting at 30,000 counts per second, consuming a total of 11 mW. The entire system is highly integrated, containing a gamma ray detector, a high voltage detector power supply, and a multichannel analyzer (MCA) system-on-a-chip (SoC), which are all combined into a compact form using a multi-level, configurable printed circuit board design. The MCA SoC, fabricated using a 65 nm CMOS technology, features two enabling resources to allow low power detections at high count rates for …

Characterization Of Low Power Hfo2 Based Switching Devices For In-Memory Computing, Aseel Zeinati

Theses

Oxide based Resistive Random Access Memory (RRAM) devices are investigated as one of the promising non-volatile memories to be used for in-memory computing that will replace the classical von Neumann architecture and reduce the power consumption. These applications required multilevel cell (MLC) characteristics that can be achieved in RRAM devices. One of the methods to achieve this analog switching behavior is by performing an optimized electrical pulse. The RRAM device structure is basically an insulator between two metals as metal-insulator-metal (MIM) structure. Where one of the primary challenges is to assign an RRAM stack with both low power consumption and …

Using An Embedded System For A Quality Cup Of Coffee, Evan Powers, Joshua Stermer, Tsion Yohannes

2023 Symposium

Many coffee lovers spend up to $5 on a cup of coffee everyday. To save money one could make them at home, but a quality machine with PIDs start at $1000. Using an embedded system one could spend less than $50 and a few hours implement PIDs into an existing $400 machine that will last a lifetime. microcontroller. Learning C language combined with hardware implementation applied to cheap and simple everyday objects can improve everyday quality of life and save money.

This is challenging because we have to incorporate the additional circuitry into a pre established circuit with limited space, …

Vi Energy-Efficient Memristor-Based Neuromorphic Computing Circuits And Systems For Radiation Detection Applications, Jorge Iván Canales Verdial

Electrical and Computer Engineering ETDs

Radionuclide spectroscopic sensor data is analyzed with minimal power consumption through the use of neuromorphic computing architectures. Memristor crossbars are harnessed as the computational substrate in this non-conventional computing platform and integrated with CMOS-based neurons to mimic the computational dynamics observed in the mammalian brain’s visual cortex. Functional prototypes using spiking sparse locally competitive approximations are presented. The architectures are evaluated for classification accuracy and energy efficiency. The proposed systems achieve a 90% true positive accuracy with a high-resolution detector and 86% with a low-resolution detector.

The Study Of Corrosion On Additive-Manufactured Metals., Braydan Daniels

Electronic Theses and Dissertations

The purpose of this study was to investigate and compare the corrosion mechanisms between wrought and additive-manufactured (3D-printed) copper and stainless steel. The experimental procedure consisted of measuring the open circuit potential, electrochemical impedance spectroscopy, linear sweep voltammetry, Tafel analysis, surface topology, and scanning electron microscopy for each metal within salt water, tap water, sulfuric acid, and synthetic body fluid (excluding copper in synthetic body fluid).

Overall, printed stainless steel was more corrosion-resistant than wrought stainless steel in tap water and synthetic body fluid based on OCP, LSV, and surface topology results. Additionally, printed copper was more corrosion-resistant than wrought …

Design And Implementation Of High-Efficiency, Lightweight, System-Friendly Solid-State Circuit Breaker, Dehao Qin

All Dissertations

Direct current (DC) distribution system has shown potential over the alternative current (AC) distribution system in some application scenarios, e.g., electrified transportation, renewable energy, data center, etc. Because of the fast response speed, DC solid-state circuit breaker (SSCB) becomes a promising technology for the future power electronics intensive DC energy system with fault-tolerant capability. First, a thorough literature survey is performed to review the DC-SSCB technology. The key components for DC-SSCB, including power semiconductors, topologies, energy absorption units, and fault detection circuits, are studied. It is observed that the prior studies mainly focus on the basic interruption capability of the …

Stream Processor Development Using Multi-Threshold Null Convention Logic Asynchronous Design Methodology, Wassim Khalil

Graduate Theses and Dissertations

Decreasing transistor feature size has led to an increase in the number of transistors in integrated circuits (IC), allowing for the implementation of more complex logic. However, such logic also requires more complex clock tree synthesis (CTS) to avoid timing violations as the clock must reach many more gates over larger areas. Thus, timing analysis requires significantly more computing power and designer involvement than in the past. For these reasons, IC designers have been pushed to nix conventional synchronous (SYNC) architecture and explore novel methodologies such as asynchronous, self-timed architecture. This dissertation evaluates the nominal active energy, voltage-scaled active energy, …