VLSI and Circuits, Embedded and Hardware Systems Commons^™

Deep Learning-Based Data-Centric Classification Of Power System Disturbances In Aerospace Systems: Software And Fpga Implementations, Ian Guzman

Doctoral Dissertations and Master's Theses

The transition toward More Electric Aircraft (MEA) has introduced highly complex electrical architectures that impose strict requirements on reliability, safety, and real‑time operation. Yet most existing research on power quality disturbances (PQDs) and electrical fault diagnosis targets conventional utility‑scale power grids and relies on low‑frequency analysis, which limits accuracy and applicability in aircraft electrical systems that operate at higher frequencies. As a result, the use of data‑driven PQD classification in aircraft power networks remains largely unexplored. This paper addresses this gap by presenting a deep learning–based framework for automated multiclass detection and classification of electrical faults and PQDs in aircraft …

Polysaber: A Custom Reactive Lightsaber Soundboard, Pedro B. Medeiros

Computer Engineering

The PolySaber project was developed as a custom reactive lightsaber control system built as a fully custom PCB design. The purpose of the project was to create a lower-cost and more customizable alternative to commercially available lightsaber soundboards while simultaneously providing hands-on experience in PCB design, embedded systems development, and hardware integration. Commercial lightsaber soundboards are expensive, proprietary, and difficult for hobbyists to customize. The PolySaber project addresses this by creating a modifiable hardware platform built around the ESP32 microcontroller. The system supports programmable firmware, RGB NeoPixel blade control, motion sensing, reactive swing and clash effects, onboard audio amplification, and …

Evaluating The Cost-Benefit Tradeoffs Of Simt Control Mechanisms In Resource-Constrained Gpus, Nikolas Tambornini

Master's Theses

This thesis conducts a hardware-level analysis of the cost–benefit tradeoffs associated with increasingly complex SIMT control mechanisms in a resource-constrained GPU core. Four design implementations are evaluated: a Base Tiny GPU without warp scheduling capability; a Warp Scheduler using round-robin warp selection; a Branch Divergence implementation incorporating a dedicated divergence stack and post-dominator reconvergence mechanism; and a Dynamic Warp Allocation implementation that replaces the static warp structure with a runtime warp manager, regrouping threads by current program counter to recover SIMD lane utilization during active divergence. Each design is evaluated using two complementary measurements: functional simulation implemented using the CocoTB …

Test Bench Pcb Design For A Vlsi Grid Cell Chip, Nicholas Bruk, Jason Alexandar

Electrical Engineering

This report presents the design, implementation, and validation of a custom printed circuit board (PCB) test bench for a VLSI grid cell emulation chip. The final board provides two independently adjustable 5V supplies using LM317 linear regulators, eleven potentiometer-controlled bias voltages, high-impedance buffering of analog outputs via an MCP6022 dual operational amplifier, and buffering of digital outputs using a 74HC244 buffer IC. The design includes a 40-pin DIP socket for the VLSI chip, extensive test-point headers for probing, and a 9V battery input for portable operation. Five fully functional boards were fabricated using ExpressPCB and assembled with through-hole components. An …

Design And Parametric Testing Of A Transimpedance Amplifier For Low-Power Biomedical Applications, Stanlon Tan, William Chung, Brandon Wu

Electrical Engineering

This project developed and evaluated an optical sensing system for detecting changes associated with glucose concentration. The system combined a laser-diode, cuvette sample holder, photodiode, resistive-feedback transimpedance amplifier, high-resolution analog-to-digital converter, and microcontroller. Parametric testing evaluated the effects of input current and feedback resistance on transimpedance gain, output range, and linearity. Firmware was developed to configure the ADC, average repeated conversions, monitor measurement variation, convert raw digital counts into voltage using a source-meter calibration equation, and compare sample measurements with a water reference. A cuvette enclosure maintained alignment between the laser-diode, sample, and photodiode while reducing external optical interference. Testing …

Simulation Of Silicon Neurons With Memristive Synapses For Ai Accelerators, Marcus Ivey, Kelvin Shi

Electrical Engineering

This project seeks to design and simulate a neuromorphic spiking neural network (SNN) that implements the logical AND and logical OR operation through the interaction of a Leaky Integrate-and-Fire (LIF) output neuron and memristive synapses modeled using the Biolek formulation. Two pulsed inputs are transmitted through memristive devices whose conductance serves as the synaptic weights. A supervised Hebbian training strategy, implemented in MATLAB, is employed to adjust the synaptic conductance according to the Hebbian delta rule. The proposed framework demonstrates how elementary logical computation may arise from biologically motivated learning processes embedded in hardware-realistic neuromorphic circuits. The study provides a …

Vlsi Spike Encoder For Spiking Neural Networks With 4-Bit Sar Adc, Jack Marshall, Wyatt Tack, Cameron Young, Ryken Thompson

Electrical Engineering

A spike encoder forms the interface between sampled data, such as image data or a sensor signal, and a spiking neural network by converting numerical input samples into discrete spike events. Unlike conventional artificial neural networks, spiking neural networks use spare, even-driven computation instead of continuous-valued activations. This makes them attractive for low-power embedded systems, biomedical electronics, and other edge applications where energy consumption, physical area, and thermal limits are important design constraints.

This project develops a modular spike encoder architecture for spiking neural networks with selectable support for temporal, rate, multi-spike, and delta encoding. Prior work has shown that …

Dot Product Engine Based Neuromorphic Hardware For Continuous-Time Biomedical Signal Classification, Sanjeev Srinivasan

Master's Theses

Accurate diagnosis of pathological conditions from biomedical signals, such as electrocardiograms (ECGs) is often performed offline, making it time-consuming, costly, and inefficient, especially when abnormal patterns are rare and long-term monitoring generates large amounts of data. To address this, this work proposes a compact, scalable, and programmable neuromorphic system designed for real-time preliminary arrhythmia detection and classification using ECG signals, that can be extended to other biomedical signals. The proposed design processes ECG signals using a delta modulation-based spike encoder, followed by classification with a dot-product engine (DPE) based spiking neural network (SNN) processor and winner-take-all (WTA) circuit. The architecture …

Holistic Dram Enhancements: From Intrinsic In-Memory Operations To Robust Security Mechanisms, Ranyang Zhou

Dissertations

Dynamic Random-Access Memory (DRAM) is both the performance bottleneck and a critical security boundary of modern computing systems. Its physical properties make it an attractive substrate for near-data computation—yet those same properties expose it to disturbance-based hardware attacks. This dissertation argues that these two dimensions are not independent: the architectural choices that make DRAM efficient also reshape its threat landscape. Addressing both requires a unified approach to memory architecture and security co-design.

The first part of this dissertation attacks the memory wall through four processing-in-DRAM (PIM) frameworks. ReD-LUT and LT-PIM unify lookup-table arithmetic with charge-sharing logic, achieving up to 37.8x …

Retinomorphic Mid-Wave Infrared In-Sensor Processing Engine: Device-To-Architecture Co-Design, Hemalatha Nagaraju

Theses

Conventional frame-based CMOS image sensors acquire full-frame pixel data at discrete time intervals, resulting in substantial spatial redundancy and loss of temporal information between frames. The repeated conversion and transfer of redundant pixel data increases bandwidth and power consumption in machine vision systems. Retinomorphic sensing architectures address these limitations by enabling programmable, analog-domain processing directly at the sensor interface. A compact behavioral model of the PbSe device is developed in HSPICE based on calibrated TCAD simulation data to capture gate-controlled photocurrent modulation under varying illumination and gate bias conditions. Error analysis is performed to quantify the deviation between TCAD-generated photocurrent …

Woodward Cuk Converter, Aditi Venkatesh, Jennifer Pereira

Honors Capstones

The purpose of this senior design project is to design and build a Cuk converter, a type of buck–boost converter. The project involves developing an analytical model and validating it through hardware testing. Cuk converters are important because they are widely used in everyday electronics, particularly in renewable energy systems such as solar power, power supplies, and electric vehicles. Their ability to increase, decrease, and reverse the polarity of voltage makes them flexible. The continuous input and output currents result in low ripple, reducing component stress and improving efficiency. To achieve these goals, simulations will be conducted using LTspice to …

Small-Scale Analog Spiking Neural Network: Design And Simulation Of An Analog Deep Neural Network, Lucas Hogue

Electrical Engineering and Computer Science Undergraduate Honors Theses

A small-scale analog schematic of a spiking neural network (SNN) is designed and demonstrated through the analog design environment (ADE) within Cadence Virtuoso. An SNN is a type of neuromorphic system that utilizes components mimicking the function of the neurons and synapses found in biological neural networks. The SNN designed in this project is composed of four layers: one input layer, two hidden layers, and one output layer. The inclusion of more than one hidden layer classifies the network as “deep” and increases the network’s efficiency at handling data with increased complexity. The SNN categorizes inputs by producing a set …

An Energy- And Area- Efficient Two-Stage Latch Comparator Using Common-Mode Reset, Larry Yu

Electrical Engineering Theses and Dissertations

This thesis presents an energy-and-area-efficient two-stage comparator implemented in TSMC 65 nm CMOS that incorporates a Floating Inverter Amplifier (FIA) followed by a latch using a common-mode reset scheme. The FIA improves input sensitivity and reduces kickback noise by isolating the input nodes from large latch voltage swings. The proposed latch resets its output nodes to a common-mode voltage rather than one of its supply rails, thereby reducing switching energy during the reset phase. The comparator can resolve differential input voltages as small as 2 mV with a clock period of 500 ps, achieving 74.33 μV input-referred noise while consuming …

A Full System Co-Simulation Platform For Evaluating Edge Machine Learning Inference Using Compute-In-Memory, Belsen Lee

Electrical Engineering and Computer Science (MS) Theses

We present a full-system co-simulation platform for evaluating embedded machine learning (ML) inference using compute-in-memory (CIM). CIM architectures aim to reduce data movement overhead by performing matrix operations in memory, but end-to-end benefits depend on system-level integration costs that are difficult to assess with isolated hardware models alone. To address this gap, we develop an integrated RISC-V QEMU-SystemC co-simulation environment that allows standard embedded Linux to interact with a transaction-level CIM accelerator model via memory-mapped I/O, direct memory access (DMA), and interrupts. To evaluate performance, we benchmark an MNIST image inference workload and a synthetic fully connected neural network, comparing …

Design And Verification Of The Multi-Slit Solar Explorer Camera Field Programmable Gate Arrays, Jordan M. Johnson

All Graduate Reports and Creative Projects, Fall 2023 to Present

The Multi-Slit Solar Explorer, or MUSE, is a NASA mission that will take images of the Sun to study solar flares and the solar corona. The mission will provide insight into the mechanisms behind space weather. The mission consists of two cameras: the Spectrograph (SG), and the Context Imager (CI). The Utah State University Space Dynamics Laboratory is providing both cameras for the mission.

This report describes a part of the design and verification process for a central component on these cameras known as the Field Programmable Gate Arrays (FPGAs). These FPGAs are programmed to acquire, handle, and send images …

Design Of An Extensible And Scalable Data Acquisition System For Pulse Shape Discrimination, Prince John

McKelvey School of Engineering Graduate Student Theses & Dissertations

This thesis presents the design and development of a highly scalable, end-to-end data acquisition (DAQ) system for nuclear physics experiments that can be deployed in configurations ranging from a few to thousands of detector channels. The system is built as an extensible platform composed of modular 16-channel chipboards that support a wide range of scintillator and detector types and perform real-time, on-board data sparsification and pulse-shape processing. Three versions of the chipboard have been fabricated to date.

The DAQ architecture is based on a family of analog pulse-shape-processing application- specific integrated circuits (ASICs) developed by the IC Design Laboratory at …

Robust Hardware Trojan Detection Leveraging Dual‑Domain Features And Stacked Ensemble Learning, Sefatun-Noor Puspa

All Theses

In Cyber-physical systems rely on sensors, communication, and computing, all powered by integrated circuits (ICs). These ICs are vulnerable to malicious hardware attacks, with hardware Trojans being one of the stealthiest threats. Trojans are malicious implants in the circuitry, which are often inserted during design or fabrication stages. This stealthy addition remains dormant until triggered and might cause functional disruptions or sensitive information leakage once triggered. Traditional IC validation methods, such as functional testing and logic analysis, usually fail to capture these subtle anomalies because hardware Trojans are intentionally designed to mimic normal circuit behavior. They often remain dormant under …

A Low-Cost Motion Classification System For A Stuffed Animal Using An Imu And Machine Learning, Rachel N. Guynes

Honors Theses

One of the many fields that has seen the integration of robots is therapy. Zoomorphic robots (ZR) are designed to look and behave like animals to assist in Animal Assisted Therapy (AAT) practices. Studies show that ZRs can provide benefits similar to working with an actual animal; however, their high cost limits their accessibility. This thesis documents the process of building a real-time, low-cost motion classification system that can be attached to a stuffed animal to make it more interactive. Using a Random Forest (RF) classifier, the system identifies movements with approximately 81.67% accuracy.

Proxyconnec: A Lora-Based Proactive Safety Communication System For Off-Grid Environments, Shruti Bhandari, Roza Shaimurat

ATU Scholars Symposium

Remote environments lacking cellular or satellite coverage present significant safety challenges. ProxyConnec was developed as a point-to-point communication system using ESP32 microcontrollers and REYAX RYLR998 LoRa modules to provide off-grid monitoring.

The system implements a proactive heartbeat model in which a beacon device transmits a signal every 1,000 milliseconds. A base station monitors this connection using a 5,000 millisecond watchdog timer. If communication is interrupted, the system immediately triggers audible and visual alerts. Unlike conventional tracking devices that depend on manual SOS activation, this design treats unexpected signal loss as a potential safety event.

The manufacturer rates the selected LoRa …

Demystifying Hardware Formal Verification For Undergraduate Education: A Risc-V Processor Case Study With Coursework Implementation, Riley A. Peters

Master's Theses

Hardware verification engineers apply formal methods to prove that a digital device always behaves according to its specification. This differs from traditional functional verification, in which engineers establish correctness by repeatedly sending test inputs to the device and comparing the outputs against a reference model. With the growing complexity of integrated circuits, the demand for digital verification engineers with formal methods experience has continued to increase. However, California Polytechnic State University: San Luis Obispo's current curriculum lacks dedicated material to prepare students for these roles.

This thesis seeks to address the lack of formal methods material through two efforts. First, …