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1045 full-text articles. Page 32 of 32.

On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm, Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman 2009 Faculty of Engineering, Technology and Built Environment UCSI University

On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm, Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

Fast Fourier transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence Efficient FFT algorithm is always considered. This paper proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating-point Arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently ...


Optimum Block Adaptive Ica For Separation Of Real And Complex Signals With Known Source Distributions In Dynamic Flat Fading Environments, Raghuram Ranganathan, Thomas Yang, Wasfy Mikhael 2009 University of Central Florida

Optimum Block Adaptive Ica For Separation Of Real And Complex Signals With Known Source Distributions In Dynamic Flat Fading Environments, Raghuram Ranganathan, Thomas Yang, Wasfy Mikhael

Thomas Yang

No abstract provided.


Adaptive Target Detection With Application To Through-The-Wall Radar Imaging, Christian Debes, Jesper Riedler, Abdelhak M. Zoubir, Moeness G. Amin 2009 AGT International

Adaptive Target Detection With Application To Through-The-Wall Radar Imaging, Christian Debes, Jesper Riedler, Abdelhak M. Zoubir, Moeness G. Amin

Christian Debes

An adaptive detection scheme is proposed for radar imaging. The proposed detector is a postprocessing scheme derived for one-, two-, and three-dimensional data, and applied to through- the-wall imaging using synthetic aperture radar. The target image statistics depend on the target three-dimensional orientation and position. The statistics can also vary with the standoff distance of the imaging system because of the change in the corresponding scene image resolution. We propose an iterative target detection scheme for the cases in which no or partial a priori knowledge of the target image statistics is available. Properties of the proposed scheme, such as ...


Vlsi Implementation Of Novel Class Of High Speed Pipelined Digital Signal Processing Filter For Wireless Receivers, Rozita Teymourzadeh, Yazan Samir, Shabuil Islam, Masuri Othman, Mok VH 2009 Faculty of Engineering, Technology and Built Environment UCSI University

Vlsi Implementation Of Novel Class Of High Speed Pipelined Digital Signal Processing Filter For Wireless Receivers, Rozita Teymourzadeh, Yazan Samir, Shabuil Islam, Masuri Othman, Mok Vh

Dr. Rozita Teymourzadeh, CEng.

The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation ...


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