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Occupancy Estimation In Smart Building Using Hybrid Co2/Light Wireless Sensor Network, Chen Mao, Qian Huang 2016 Department of Electrical and Computer

Occupancy Estimation In Smart Building Using Hybrid Co2/Light Wireless Sensor Network, Chen Mao, Qian Huang

ASA Multidisciplinary Research Symposium

Smart building, which delivers useful services to residents at lowest cost and maximum comfort, has gained increasing attention in recent years. A variety of emerging information technologies have been adopted in modern buildings, such as wireless sensor networks, internet of things, big data analytics, deep machine learning, etc. Most people agree that a smart building should be energy efficient, and consequently, much more affordable to building owners. Building operation accounts for major portion of energy consumption in the United States. HVAC (heating, ventilating, and air conditioning) equipment is a particularly expensive and energy consuming of building operation. As a result ...


Reward Modulated Spike Timing Dependent Plasticity Based Learning Mechanism In Spiking Neural Networks, Shrihari Sridharan, Gopalakrishnan Srinivasan, Kaushik Roy 2016 Purdue University

Reward Modulated Spike Timing Dependent Plasticity Based Learning Mechanism In Spiking Neural Networks, Shrihari Sridharan, Gopalakrishnan Srinivasan, Kaushik Roy

The Summer Undergraduate Research Fellowship (SURF) Symposium

Spiking Neural Networks (SNNs) are one of the recent advances in machine learning that aim to further emulate the computations performed in the human brain. The efficiency of such networks stems from the fact that information is encoded as spikes, which is a paradigm shift from the computing model of the traditional neural networks. Spike Timing Dependent Plasticity (STDP), wherein the synaptic weights interconnecting the neurons are modulated based on a pair of pre- and post-synaptic spikes is widely used to achieve synaptic learning. The learning mechanism is extremely sensitive to the parameters governing the neuron dynamics, the extent of ...


Low-Noise Micro-Power Amplifiers For Biosignal Acquisition, Tan Yang 2016 University of Tennessee, Knoxville

Low-Noise Micro-Power Amplifiers For Biosignal Acquisition, Tan Yang

Doctoral Dissertations

There are many different types of biopotential signals, such as action potentials (APs), local field potentials (LFPs), electromyography (EMG), electrocardiogram (ECG), electroencephalogram (EEG), etc. Nerve action potentials play an important role for the analysis of human cognition, such as perception, memory, language, emotions, and motor control. EMGs provide vital information about the patients which allow clinicians to diagnose and treat many neuromuscular diseases, which could result in muscle paralysis, motor problems, etc. EEGs is critical in diagnosing epilepsy, sleep disorders, as well as brain tumors.

Biopotential signals are very weak, which requires the biopotential amplifier to exhibit low input-referred noise ...


Area And Delay Efficient Carry Select Adder Using Carry Prediction Approach, Satinder Singh Mohar, Manjit Singh Bhamrah 2016 Punjabi University, Patiala, Punjab, India

Area And Delay Efficient Carry Select Adder Using Carry Prediction Approach, Satinder Singh Mohar, Manjit Singh Bhamrah

Kirat Pal Singh

Various approaches and designs of digital arithmetic units have been proposed in the recent years and their merits and demerits have been compared on various performance parameters. In modern day digital systems, Arithmetic and Logic Unit operations on reconfigurable devices are the most important area of research. In this paper, a novel design for Carry Select Adder is proposed. In the design, the half adder of both the ripple carry adders is shared and an initial sum and carry is generated. The carry input module generates the ‘carry’ values and are passed through multiplexer in first method or xor-ed with ...


Analog Vlsi Circuit Design: Linear Voltage Regulator, Brett Colteaux, Kirstie Fung 2016 California Polytechnic State University, San Luis Obispo

Analog Vlsi Circuit Design: Linear Voltage Regulator, Brett Colteaux, Kirstie Fung

Electrical Engineering

The project outlined in this report is the design, layout, and routing of a linear voltage regulator using Cadence VLSI (very-large-scale integration) software. The design specifications for this regulator are as follows: input voltage range of 5V + 1V, load current capabilities of 150mA, and output voltage range of 1.15V to 3.3V. Furthermore, the design of this circuit was broken into three main sub-circuits: an error amplifier, bandgap reference circuitry, and biasing circuitry for the bandgap. Together, these sub-circuits integrated to make the final design.

Research for different topologies for a voltage regulator was done and the Brokaw bandgap ...


Design Of An Integrated Acceleration Acquisition Subsystem To Satisfy High-Speed And Low-Area Requirements For Cubesats, Ryan J. Rumsey 2016 California Polytechnic State University, San Luis Obispo

Design Of An Integrated Acceleration Acquisition Subsystem To Satisfy High-Speed And Low-Area Requirements For Cubesats, Ryan J. Rumsey

Master's Theses and Project Reports

Cal Poly San Luis Obispo’s PolySat team is designing the Multipurpose Orbital Spring Ejection System (MOSES) in order to record acceleration data during the launch of CubeSats as well as to provide GPS coordinates to locate the position of CubeSats once they are injected into orbit. This work focuses on the design and development of the acceleration data acquisition (DAQ) subsystem of MOSES. This subsystem is designed around the need for a high-speed sampling system of at least 200 kHz across four channels of data, plus low-area limitations in the MOSES form factor which is roughly half the size ...


A Stroke Therapy Brace Design, Evan Kirkbride 2016 California Polytechnic State University, San Luis Obispo

A Stroke Therapy Brace Design, Evan Kirkbride

Electrical Engineering

Victims of stroke often have difficulty with rehabilitation. With limited movement on their affected arm, patients often do not want to move much for physical therapy. In this project, we design a robotic brace that helps stroke patients move their arm more effectively in a reaching or pulling motion. By giving patients more movement in their affected arm than they would have otherwise, patients gain more from rehabilitation. The brace also adapts to the patient’s needs, providing more inclination or resistance as needed for their physical therapy. This kind of therapy engages patients rather than relying on their likely ...


Cal Poly Supermileage Electronic Fuel Injection, Alexander Pink 2016 California Polytechnic State University, San Luis Obispo

Cal Poly Supermileage Electronic Fuel Injection, Alexander Pink

Electrical Engineering

Cal Poly Supermileage is a student-run engineering club that builds prototype gasoline vehicles optimized maximum fuel-efficiency. To power their vehicles, the Supermileage team makes use of single-cylinder, 4-stroke, electronically fuel-injected (EFI) gasoline engines. This report details the development, iterative design & test cycles, and integration of an EFI system for the Supermileage club. This project develops an EFI system that interfaces to the most common types of sensors found in the low-power Supermileage-range of engines, including throttle-position sensors, manifold absolute pressure sensors, gear-tooth hall-effect sensors, variable-reluctance position sensors, engine coolant temperature sensors, intake air temperature sensors, and exhaust oxygen sensors. This ...


El Capitán: Cal Poly Rose Float Digital Drive System, Gregory Raffi Baghdikian 2016 California Polytechnic State University, San Luis Obispo

El Capitán: Cal Poly Rose Float Digital Drive System, Gregory Raffi Baghdikian

Computer Engineering

In today’s world of smartphones, self-driving cars, and internet-connected coffee makers, it seems as if computers are contained in everything around us. These “embedded systems” have become critical components of our lives, improving everything about the things they control, from cost, to speed, to simplicity. One area that embedded systems has hardly gained a foothold is in the world of floatbuilding. Most of the floats in the Tournament of Roses Parade, including the one built jointly by Cal Poly San Luis Obispo and Cal Poly Pomona, are technologically very simple, using mostly analog components and rudimentary discrete digital logic ...


Implementation Of Discrete Wavelet Transform In Soc Using Vedic Mathematics, R. Nirmala, K. Sathiya Sekar 2016 Vivekanandha College of Engineering for Women, Ellayampalayam, Tiruchengode

Implementation Of Discrete Wavelet Transform In Soc Using Vedic Mathematics, R. Nirmala, K. Sathiya Sekar

Kirat Pal Singh

A new design for the implementation of discrete wavelet transform in system on chip(SoC) using vedic mathematics has been proposed. The proposed design incorporates the efficiency of Vedic mathematics and low power consumption through 90nm technology in the SoC design. The study presents a design methodology for a custom ASIC Processor core for signal and image processing application with highest performance and lowest part cost. The system on chip is designed in 90 nm technology and consists of a MAC unit, SRAM and buffers The design mainly focused on the processor core block which is implemented using a MAC ...


Design Of Low Power And High Speed Carry Select Adder Using 32-Bit Brent Kung Adder, Gaddam Vidyavathi, Upendranath Goud 2016 G.Pullaiah College of Engineering & Technology, Kurnool

Design Of Low Power And High Speed Carry Select Adder Using 32-Bit Brent Kung Adder, Gaddam Vidyavathi, Upendranath Goud

Kirat Pal Singh

The binary addition is the basic arithmetic operation in digital circuits and it became essential in most of the digital systems including Arithmetic and Logic Unit (ALU), microprocessors and Digital Signal Processing (DSP).In this paper, Carry Select Adder (CSA) architectures are proposed using parallel prefix adders. Instead of using dual Ripple Carry Adders (RCA), parallel prefix adder i.e., Brent Kung (BK) adder is used to design Regular Linear CSA. Adders are the basic building blocks in digital integrated circuit based designs. Ripple Carry Adder (RCA) gives the most compact design but takes longer computation time. The time critical ...


Review On: Performance Optimization Of Csla Using Hca, Ashish V. Ughade, Rajal H. Deshmukh, Akshay P. Nanote 2016 SDCOE, Selukate, Wardha

Review On: Performance Optimization Of Csla Using Hca, Ashish V. Ughade, Rajal H. Deshmukh, Akshay P. Nanote

Kirat Pal Singh

Adders form an almost obligatory component of every contemporary integrated circuit. There are different kinds of adder available out of which Carry Select Adder (CSLA) having best performance parameters. At present there is regular SQRT CSLA structure, in which the second level of SQRT is replaced by the Binary to Excess–I Converter (BEC) but still there is possibility to get better design in which optimization of area, delay is to be major concentrations as well as power requirement. RCA at its first level of CSLA requires more area. Hence
this paper proposes CSLA with Han Carlson adder instead of ...


Performance Comparison Of Carry Select Adders, Nithin Bidare Puttaraju, Mr. Adithya 2016 Global Academy of Technology, Karnataka, India

Performance Comparison Of Carry Select Adders, Nithin Bidare Puttaraju, Mr. Adithya

Kirat Pal Singh

Adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data-processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Modified Carry select adder (MCSLA) and proposed CSLA, in terms ...


Design Of High Speed Power Efficient Wallace Tree Adders, Sakshi Sharma, Pallavi Thakur 2016 University College of Engineering, Punjabi University, Patiala, Punjab, India

Design Of High Speed Power Efficient Wallace Tree Adders, Sakshi Sharma, Pallavi Thakur

Kirat Pal Singh

In this paper FIFB, FIEB and FISB Carry Save Adders and Wallace Tree Adders are designed, encoded in Verilog and simulated using Cadence Software. The 180 nm CMOS technology is used for implementation of adders.The simulation results are compared for power consumption, delay, silicon area and dynamic power dissipation. As the length of inputs increase, power dissipated, silicon area and delay increase in both Carry Save Adder and Wallace Tree Adder. Compared to traditional CSA, the proposed Wallace Tree Adder is found to have shorter delay, lesser power dissipation and lesser silicon area and hence more cost efficient and ...


Design Of Carry Select Adder Using Binary To Excess-3 Converter In Vhdl, Brijesh Kumar, Mamta Kulkarni 2016 Vaagdevi college of engg. Pune, Andra Pradesh, India

Design Of Carry Select Adder Using Binary To Excess-3 Converter In Vhdl, Brijesh Kumar, Mamta Kulkarni

Kirat Pal Singh

This paper presents a modified design of Area-Efficient Low power Carry Select Adder (CSLA) Circuit. In digital adders, the speed of addition is limited by the time required to transmit a carry through the adder. Carry select adder processors and systems. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The major speed limitation in any adder is in ...


Implementation Of Efficient Carry Select Adder On Fpga, Balaji Goswami, Ms. Priya, B. Rajanh 2016 RajLakshmi Engineering College, Tamil Nadu, India

Implementation Of Efficient Carry Select Adder On Fpga, Balaji Goswami, Ms. Priya, B. Rajanh

Kirat Pal Singh

In this paper, we have proposed a modified carry select adder which is known as fastest adders that can perform arithmetic operations in Digital signal processors. Modification in the gate level of the Square root Carry Select Adder (SQRT CSLA) structure results in the reduction of area and power of the CSLA structure which offers a simple and efficient function. Depending upon the Regular SQRT CSLA, we have modified the structure of the adders. The proposed design for 128-bit modified CSLA has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the ...


Comparison Of 32-Bit Ripple Carry Adder And Carry Look-Ahead Adder In Vhdl, Viraj V. Gotmare, Pankaj AGRAWAL 2016 G. H. Raisoni Academy of Engineering and Tech., Nagpur, Maharashtra, India

Comparison Of 32-Bit Ripple Carry Adder And Carry Look-Ahead Adder In Vhdl, Viraj V. Gotmare, Pankaj Agrawal

Kirat Pal Singh

The paper describes the comparison between the 32-bit ripple carry adder (RCA) and 32- bit carry look-ahead adder (CLA). Adders are used in many data-processing systems to perform fast arithmetic operations. The ripple carry adder (RCA) gives the most compact design but takes longer computation time. The time critical applications use carry look-ahead adder (CLA) to derive fast result but least to increase in area. In this work we compared both adders on the basis of delay, power and area. This design has been synthesized by Spartan 3 family with XC3S400 device.


Design And Implementation Of An Integrated Biosensor Platform For Lab-On-A-Chip Diabetic Care Systems, Khandaker Abdullah Al Mamun 2016 University of Tennessee - Knoxville

Design And Implementation Of An Integrated Biosensor Platform For Lab-On-A-Chip Diabetic Care Systems, Khandaker Abdullah Al Mamun

Doctoral Dissertations

Recent advances in semiconductor processing and microfabrication techniques allow the implementation of complex microstructures in a single platform or lab on chip. These devices require fewer samples, allow lightweight implementation, and offer high sensitivities. However, the use of these microstructures place stringent performance constraints on sensor readout architecture. In glucose sensing for diabetic patients, portable handheld devices are common, and have demonstrated significant performance improvement over the last decade. Fluctuations in glucose levels with patient physiological conditions are highly unpredictable and glucose monitors often require complex control algorithms along with dynamic physiological data. Recent research has focused on long term ...


Implementation Of The Continuous Space Language Model On A Heterogeneous Mobile Processor, Kurt Spencer Shively 2016 Indiana University - Purdue University Fort Wayne

Implementation Of The Continuous Space Language Model On A Heterogeneous Mobile Processor, Kurt Spencer Shively

Masters' Theses

Mobile processors continue to increase in performance while becoming more power efficient, providing consumers with improved gaming, multi-media, and browsing, along with longer lasting device usage. To keep up with consumer multimedia demand, mobile processor manufacturers have begun to integrate Graphical Processing Units (GPU) on mobile processors, providing users with the high performance graphics required for mobile gaming applications. The addition of integrated GPUs to the mobile processors also offers new opportunities for introducing to the mobile platform computationally intensive algorithms that were formerly impractical when running on the mobile CPU processor alone. GPU manufacturers such as NVIDIA are scaling ...


Performance Analysis For Full Adder With Zipper Logic, Bhawna Kankane, Sandeep Sharma, Navaid Rizvi 2016 Gautam Buddha University, Greater Noida, India

Performance Analysis For Full Adder With Zipper Logic, Bhawna Kankane, Sandeep Sharma, Navaid Rizvi

Kirat Pal Singh

with the shrinking technology, new systems are designed that are miniature in size and perform faster operations. Adder is a basic circuit used for the purpose of addition. In a cascade design, the output of one circuit acts as an input for the other, so delay in the propagation of the carry generated while addition is major issue in the design of adders. When the circuit is designed with any other logic the problem may arise with stored values. During pre-charge, the stored output can affect the circuit. In this paper, we propose Zipper logic for adder circuit so that ...


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