The Effect Of The Digit Slicing Architecture On The Fft Butterfly,
Yazan Samir, Rozita Teymourzadeh
2009
Faculty of Engineering, Technology and Built Environment UCSI University
The Effect Of The Digit Slicing Architecture On The Fft Butterfly, Yazan Samir, Rozita Teymourzadeh
Dr. Rozita Teymourzadeh, CEng.
Most communications systems tend to achieve bandwidth, power and cost efficiencies to capable to describe modulation scheme. Hence for signal modulation orthogonal frequency division multiplexing (OFDM) transceiver is introduced to cover communications demand in four generation. However high performance Fast Fourier Transforms (FFT) as a main heart of OFDM acts beyond the view. In order to achieve capable FFT, design and realization of its efficient internal structure is key issues of this research work. In this paper implementation of high performance butterfly for FFT by applying digit slicing technique is presented. The proposed design focused on the trade-off between the …
Vlsi Implementation Of Novel Class Of High Speed Pipelined Digital Signal Processing Filter For Wireless Receivers,
Rozita Teymourzadeh, Yazan Samir, Shabuil Islam, Masuri Othman, Mok VH
2009
Faculty of Engineering, Technology and Built Environment UCSI University
Vlsi Implementation Of Novel Class Of High Speed Pipelined Digital Signal Processing Filter For Wireless Receivers, Rozita Teymourzadeh, Yazan Samir, Shabuil Islam, Masuri Othman, Mok Vh
Dr. Rozita Teymourzadeh, CEng.
The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation …
Design Of Automatic Soil Humidity Control Using Maximum Power Point Tracking Controller,
Hoe CK, Vaithlingam A.C., Rozita Teymourzadeh, Rajkumar R
2009
Faculty of Engineering, Technology and Built Environment UCSI University
Design Of Automatic Soil Humidity Control Using Maximum Power Point Tracking Controller, Hoe Ck, Vaithlingam A.C., Rozita Teymourzadeh, Rajkumar R
Dr. Rozita Teymourzadeh, CEng.
The photovoltaic system uses the photovoltaic array as a source of electrical power for the direct conversion of the sun’s radiation to direct current without any environmental hazards. The main purpose of this research is to design of a converter with Maximum Power Point Tracker (MPPT) algorithm for any typical application of soil humidity control. Using this setup the major energy from the solar panel is used for the control of soil humidity. The design of the converter with MPPT together with the soil humidity control logic is presented in this paper. Experimental testing of the design controller is implemented …
On-Chip Implementation Of Pipeline Digit-Slicing Multiplier-Less Butterfly For Fast Fourier Transform Architecture,
Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam, Mok VH
2009
Faculty of Engineering, Technology and Built Environment UCSI University
On-Chip Implementation Of Pipeline Digit-Slicing Multiplier-Less Butterfly For Fast Fourier Transform Architecture, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam, Mok Vh
Dr. Rozita Teymourzadeh, CEng.
The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This study presents on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly, digit-slicing multiplier-less single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT) FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was …
On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm,
Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman
2009
Faculty of Engineering, Technology and Built Environment UCSI University
On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm, Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman
Dr. Rozita Teymourzadeh, CEng.
Fast Fourier transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence Efficient FFT algorithm is always considered. This paper proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating-point Arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently, synthesis report …
