Characterization Of The 5 Ghz Elevator Shaft Channel, 2013 University of South Carolina - Columbia
Characterization Of The 5 Ghz Elevator Shaft Channel, Ruoyu Sun, David W. Matolak
Faculty Publications
In this paper we provide channel characterization results for the elevator shaft channel in the 5-GHz band, based upon measurements conducted in four buildings. This channel is of interest for several applications, including WiFi and public safety. Although several authors have provided elevator shaft channel characteristics for lower-frequency bands (255-MHz, 900-MHz, 1.9-GHz), to our knowledge this is the first work that addresses the 5-GHz band. Moreover, prior work has not thoroughly addressed channel characteristics when the elevator car is in motion, whereas here we provide measurement and modeling results for this dynamic condition. Our measurements were of power delay profiles, …
Piezoelectric Transformer And Hall-Effect Based Sensing And Disturbance Monitoring Methodology For High-Voltage Power Supply Lines, 2013 The University of Western Ontario
Piezoelectric Transformer And Hall-Effect Based Sensing And Disturbance Monitoring Methodology For High-Voltage Power Supply Lines, Sneha Arun Lele
Electronic Thesis and Dissertation Repository
Advancements in relaying algorithms have led to an accurate and robust protection system widely used in power distribution. However, in low power sections of relaying systems, standard voltage and current measurement techniques are still used. These techniques have disadvantages like higher cost, size, electromagnetic interference, resistive losses and measurement errors and hence provide a number of opportunities for improvement and integration. We present a novel microsystem methodology to sense low-power voltage and current signals and detect disturbances in high-voltage power distribution lines. The system employs dual sensor architecture that consists of a piezoelectric transformer in combination with Hall-effect sensor, used …
Brief Comparison Between 8051 And Avr, 2013 University of Pune
Brief Comparison Between 8051 And Avr, Ata Jahangir Moshayedi
Ata Jahangir Moshayedi
Brief comparison between 8051 and AVR
Analysis Of Parameter Tuning On Energy Efficiency In Asynchronous Circuits, 2013 University of Arkansas, Fayetteville
Analysis Of Parameter Tuning On Energy Efficiency In Asynchronous Circuits, Justin Thomas Roark
Graduate Theses and Dissertations
Power and energy consumption are the primary concern of the digital integrated circuit (IC) industry. Asynchronous logic, in the past several years, has increased in popularity due to its low power nature. This thesis analyzes a collection of array multipliers with different parameters to compare two asynchronous design paradigms, NULL Convention Logic (NCL) and Multi-Threshold NULL Convention Logic (MTNCL). Several commercially available pieces of software and custom scripts are used to analyze the asynchronous circuits and their components to provide the energy consumption estimation on various parts of each circuit. The analysis of the software results revealed that MTNCL circuits …
Cad Tool Design For Ncl And Mtncl Asynchronous Circuits, 2013 University of Arkansas, Fayetteville
Cad Tool Design For Ncl And Mtncl Asynchronous Circuits, Vijay Mani Pillai
Graduate Theses and Dissertations
This thesis presents an implementation of a method developed to readily convert Boolean designs into an ultra-low power asynchronous design methodology called MTNCL, which combines multi-threshold CMOS (MTCMOS) with NULL Convention Logic (NCL) systems. MTNCL provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. The proposed tool utilizes industry-standard CAD tools. This research also presents an Automated Gate-Level Pipelining with Bit-Wise Completion (AGLPBW) method to maximize throughput of delay-insensitive full-word pipelined NCL circuits. These methods have been integrated into the Mentor Graphics and …
A Secure Reconfigurable System-On-Programmable-Chip Computer System, 2013 University of Tennessee - Knoxville
A Secure Reconfigurable System-On-Programmable-Chip Computer System, William Herbert Collins
Masters Theses
A System-on-Programmable-Chip (SoPC) architecture is designed to meet two goals: to provide a role-based secure computing environment and to allow for user reconfiguration. To accomplish this, a secure root of trust is derived from a fixed architectural subsystem, known as the Security Controller. It additionally provides a dynamically configurable single point of access between applications developed by users and the objects those applications use. The platform provides a model for secrecy such that physical recovery of any one component in isolation does not compromise the system. Dual-factor authentication is used to verify users. A model is also provided for tamper …
Delay Extraction Based Macromodeling With Parallel Processing For Efficient Simulation Of High Speed Distributed Networks, 2013 The University of Western Ontario
Delay Extraction Based Macromodeling With Parallel Processing For Efficient Simulation Of High Speed Distributed Networks, Sourajeet Roy
Electronic Thesis and Dissertation Repository
This thesis attempts to address the computational demands of accurate modeling of high speed distributed networks such as interconnect networks and power distribution networks. In order to do so, two different approaches towards modeling of high speed distributed networks are considered. One approach deals with cases where the physical characteristics of the network are not known and the network is characterized by its frequency domain tabulated data. Such examples include long interconnect networks described by their Y parameter data. For this class of problems, a novel delay extraction based IFFT algorithm has been developed for accurate transient response simulation.
The …
Data Driven Feed Forward Adaptive Testing, 2013 Portland State University
Data Driven Feed Forward Adaptive Testing, Chaitrali Santosh Chandorkar
Dissertations and Theses
Test cost is a critical component in the overall cost of the product. Test cost varies in direct proportion with test time. This thesis introduces a data driven feed forward adaptive technique for reducing test time at wafer sort while maintaining the product defect level. Test data from first insertion of wafer is statistically analyzed to make a decision about adaptive test flow at subsequent insertions.
The data driven feed forward technique uses a statistical screen to analyze test data from first probe of wafer and provides recommendations for test elimination at second insertions. At the second insertion dies are …
Poly_Sense: Modular Wireless Sensor Network, 2013 California Polytechnic State University - San Luis Obispo
Poly_Sense: Modular Wireless Sensor Network, Ian Andal, James Shirley, Haleigh Vierra
Electrical Engineering
Poly_Sense provides a platform for developers to use for a wide range of Wireless Sensor Network (WSN) applications. This modular system supports different sensing applications by allowing the developer to easily change between supported sensors through the graphical user interface (GUI). The platform also allows developers to integrate new sensors by writing device drivers which follow the platform’s guidelines and utilize the application programming interface (API). This low-power and cost-effective wireless solution not only provides a basic platform for entry-level developers, but also accommodates larger-scale applications.
Monophonic Pitch Recognition, 2013 California Polytechnic State University - San Luis Obispo
Monophonic Pitch Recognition, Nathan Zorndorf, Kristine Carreon
Electrical Engineering
The purpose of this project is to create a system that automatically converts monophonic music into its MIDI equivalent. Automatic pitch recognition allows for numerous commercial applications, including automatic transcription and digital storage of live performances. It is also desirable to be able to take an audio signal as an input and create a MIDI equivalent score because the MIDI information can be used to replace the original audio signal sounds with any sound the user would like. For example, if a piano composition is entered into the system, the resulting MIDI out could be used to trigger guitar samples. …
The Bicycle-Powered Smartphone Charger, 2013 California Polytechnic State University, San Luis Obispo
The Bicycle-Powered Smartphone Charger, Chris Arntzen
Master's Theses
This thesis entails the design and fabrication of a smartphone charger that is powered by a bicycle dynamo hub. In addition to the design and validation of the charger prototype, this thesis involves the testing and characterization of the dynamo hub power source, the design and construction of specialized test equipment, and the design and prototyping of a handlebar-mounted case for the smartphone and charging electronics. With the intention of making the device a commercial product, price, aesthetics, and marketability are of importance to the design. An appropriate description of the charger circuit is a microcontroller-based energy management system, tailored …
Design And Evaluation Of Fpga-Based Hybrid Physically Unclonable Functions, 2013 The University of Western Ontario
Design And Evaluation Of Fpga-Based Hybrid Physically Unclonable Functions, Sasan Khoshroo
Electronic Thesis and Dissertation Repository
A Physically Unclonable Function (PUF) is a new and promising approach to provide security for physical systems and to address the problems associated with traditional approaches. One of the most important performance metrics of a PUF is the randomness of its generated response, which is presented via uniqueness, uniformity, and bit-aliasing. In this study, we implement three known PUF schemes on an FPGA platform, namely SR Latch PUF, Basic RO PUF, and Anderson PUF. We then perform a thorough statistical analysis on their performance. In addition, we propose the idea of the Hybrid PUF structure in which two (or more) …
Automated Behavioral Modeling Of Switching Voltage Regulators, 2013 University of Arkansas, Fayetteville
Automated Behavioral Modeling Of Switching Voltage Regulators, Michael Leonard
Electrical Engineering Undergraduate Honors Theses
This work describes the development of a software tool that implements a novel method for automatically generating simulation ready behavioral models for switching circuits with an emphasis on power regulators. The work begins by examining the theory of operation of both linear and switching regulators. Then, the capability of two behavioral modeling languages (Verilog-A and PSPICE ABM) are examined in detail. Next, the languages previously discussed are used to develop and test a model of a commercial regulator (Texas Instruments TPS40305). Finally, the prospect of automating the process is discussed
Design, Layout, And Testing Of A Silicon Carbide-Based Under Voltage Lock-Out Circuit, 2013 University of Arkansas, Fayetteville
Design, Layout, And Testing Of A Silicon Carbide-Based Under Voltage Lock-Out Circuit, Michael Dalan Glover
Graduate Theses and Dissertations
Silicon carbide-based power devices play an increasingly important role in modern power conversion systems. Finding a means to reduce the size and complexity of these systems by even incremental amounts can have a significant impact on cost and reliability. One approach to achieving this goal is the die-level integration of gate driver circuitry with the SiC power devices. Aside from cost reductions, there are significant advantages to the integration of the gate driver circuits with the power devices. By integrating the gate driver circuitry with the power devices, the parasitic inductances traditionally seen between the gate driver and the switching …
Cad Tools For Synthesis Of Sleep Convention Logic, 2013 University of Arkansas, Fayetteville
Cad Tools For Synthesis Of Sleep Convention Logic, Parviz Palangpour
Graduate Theses and Dissertations
This dissertation proposes an automated flow for the Sleep Convention Logic (SCL) asynchronous design style. The proposed flow synthesizes synchronous RTL into an SCL netlist. The flow utilizes commercial design tools, while supplementing missing functionality using custom tools. A method for determining the performance bottleneck in an SCL design is proposed. A constraint-driven method to increase the performance of linear SCL pipelines is proposed. Several enhancements to SCL are proposed, including techniques to reduce the number of registers and total sleep capacitance in an SCL design.
Wireless Transmission Network : A Imagine, 2013 Rajasthan Technical University Kota
Wireless Transmission Network : A Imagine, Radhey Shyam Meena Engineer, Neeraj Kumar Garg Asst.Prof
Radhey Shyam Meena
World cannot be imagined without electrical power. Generally the power is transmitted through transmission networks. This paper describes an original idea to eradicate the hazardous usage of electrical wires which involve lot of confusion in particularly organizing them. Imagine a future in which wireless power transfer is feasible: cell phones, household robots, mp3 players, laptop computers and other portable electronic devices capable of charging themselves without ever being plugged in freeing us from that final ubiquitous power wire. This paper includes the techniques of transmitting power without using wires with an efficiency of about 95% with non-radioactivemethods. In this paper …
Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, 2013 University of Nevada, Las Vegas
Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker
College of Engineering: Graduate Celebration Programs
As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. Although Static-Timing Analysis (STA) remains an excellent tool, current trends in process scaling have imposed significant difficulties to STA. As one of the promising solutions, Statistical static timing analysis (SSTA) has become the frontier research topic in recent years in combating such variation effects. This poster will be focusing on two aspects of SSTA and its applications in VLSI designs: (1) Statistical timing modeling and analysis; and (2) Architectural implementations of the atomic operations (max and add) using …
Structural Data Acquisition Using Sensor Network, 2013 Florida International University
Structural Data Acquisition Using Sensor Network, Sainath Chidambar Munavalli
FIU Electronic Theses and Dissertations
The development cost of any civil infrastructure is very high; during its life span, the civil structure undergoes a lot of physical loads and environmental effects which damage the structure. Failing to identify this damage at an early stage may result in severe property loss and may become a potential threat to people and the environment. Thus, there is a need to develop effective damage detection techniques to ensure the safety and integrity of the structure. One of the Structural Health Monitoring methods to evaluate a structure is by using statistical analysis. In this study, a civil structure measuring 8 …
Battery Energy Storage System In Solar Power Generation, 2013 Rajasthan Technical University Kota
Battery Energy Storage System In Solar Power Generation, Radhey Shyam Meena Er., Deepa Sharma
Radhey Shyam Meena
Grid-connected solar PV dramatically changes the load profile of an electric utility customer. The expected widespread adoption of solar generation by customers on the distribution system poses significant challenges to system operators both in transient and steady state operation, from issues including voltage swings, sudden weather-induced changes in generation, and legacy protective devices designed with one-way power flow in mind
Greek Patent Protection System And The Impacts Of Information Technology Industry, 2013 Seoul National University
Greek Patent Protection System And The Impacts Of Information Technology Industry, Emmanouil Alexander Zografakis Ez
Emmanouil Alexander Zografakis EZ
Our era can be characterized as the era of knowledge proliferation and bountifulness. That has marked our era as the era following the pace of the Information Society Development. Information Society has also brought about a remarkable IT development pace over countries. Thereby, it is greatly important all that raw knowledge to become mind figments, ideas and even inventions and innovations. It is also essential to highlight that such a beneficial process will ensure the continuity of the IT development. The only way to achieve that goal is to find a way to secure all that aforementioned knowledge which is …