VLSI and Circuits, Embedded and Hardware Systems Commons^™

International Conference On Electronics & Communication Engineering, Prof.Srikanta Patnaik Mentor

Conference Proceedings - Full Volumes

International Conference on Electronics and Communication Engineering (ICECE-2012) provides such unique platform for R&D works. The conference will conglomerate academicians, researchers from all types of institutions and organizations who would share their domain knowledge and healthy interaction would take place covering the areas like electronics and communications engineering, electric energy, automation, control and instrumentation, computer and information technology, and the electrical engineering aspects of building services and aerospace engineering, The wide scope encompasses analogue and digital circuit design, microwave circuits and systems, optoelectronic circuits, photo voltaic, semiconductor devices, sensor technology, transport in electronic materials, VLSI technology and device processing.

Ultra-Low Power And Radiation Hardened Asynchronous Circuit Design, Liang Zhou

Graduate Theses and Dissertations

This dissertation proposes an ultra-low power design methodology called bit-wise MTNCL for bit-wise pipelined asynchronous circuits, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. It provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. It was enhanced to handle indeterminate standby states. The original MTNCL concept was enhanced significantly by sleeping Registers and Completion Logic as well as Combinational circuits to reduce area, leakage power, and energy per operation.

This dissertation also develops an architecture that allows NCL …

Characterization And Modeling Of 4h-Sic Low Voltage Mosfets And Power Mosfets, Mihir Mudholkar

Graduate Theses and Dissertations

The integration of low voltage and high voltage circuits on SiC has profound applications. SiC power devices have proved their superiority in terms of high temperature operation, faster switching frequencies and larger power densities when compared with Si power devices. The control of SiC power devices however, lies in the hands of low voltage circuits built on Si. Thus, there exists a separation in the overall system between the low voltage and high voltage side, which increases system cost, weight and reduces efficiency. With the advancement in low voltage SiC processing technology, low voltage control circuits can be made on …

Silicon Germanium Sram And Rom Designs For Wide Temperature Range Space Applications, Matthew Barlow

Graduate Theses and Dissertations

This thesis presents a design flow from specifications and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1 kilobyte that are suitable for lunar environments. The design uses the IBM SiGe 5AM BiCMOS 0.5 micron process for a synchronous memory system capable of operating at a clock frequency of 25 MHz. Radiation mitigation techniques are discussed and implemented to harden the design against total ionizing dose (TID), single-event upset (SEU), and single-event latch-up (SEL). The memory arrays are also designed to operate over the wide temperature range of -180 °C to 125 °C. Design, …

Experimental Study Of Novel Materials And Module For Cryogenic (4k) Superconducting Multi-Chip Modules, Ranjith John

Graduate Theses and Dissertations

The objectives of this proposal are to understand the science and technology of interfaces in the packaging of superconducting electronic (SCE) multichip modules (MCMs) at 4 K. The thermal management issue of the current SCE-MCMs was examined and the package assembly was optimized. A novel thermally conducting and electrically insulating nano-engineered polymer was developed for the thermal management of SCE-MCMs for 4 K cryogenic packaging. Finally, the nano-engineered polymer was integrated as underfill in a SCE-MCM and the thermal and electrical performance of SCE-MCM was demonstrated at 4 K.

Niobium based superconducting electronics (SCE) are the fastest known digital logic …

Power Aware Computing On Gpus, Kiran Kumar Kasichayanula

Masters Theses

Energy and power density concerns in modern processors have led to significant computer architecture research efforts in power-aware and temperature-aware computing. With power dissipation becoming an increasingly vexing problem, power analysis of Graphical Processing Unit (GPU) and its components has become crucial for hardware and software system design. Here, we describe our technique for a coordinated measurement approach that combines real total power measurement and per-component power estimation. To identify power consumption accurately, we introduce the Activity-based Model for GPUs (AMG), from which we identify activity factors and power for microarchitectures on GPUs that will help in analyzing power tradeoffs …

Proceedings Of International Conference On Electrical And Electronics Engineering, Prof.Srikanta Patnaik Mentor

Conference Proceedings - Full Volumes

Welcome to the official website of the International Conference on Electrical and Electronics Engineering (ICEEE). ICEEE aims to bring together researchers, scientists, engineers, and scholar students to exchange and share their experiences, new ideas, and research results about all aspects of Electrical and Electronics engineering and Technology, and discuss the practical challenges encountered and the solutions adopted. The conference will be held every year to make it an ideal platform for people to share views and experiences in Electrical and Electronics Engineering and related areas.

Low-Voltage Bulk-Driven Amplifier Design And Its Application In Implantable Biomedical Sensors, Liang Zuo

Doctoral Dissertations

The powering unit usually represents a significant component of the implantable biomedical sensor system since the integrated circuits (ICs) inside for monitoring different physiological functions consume a great amount of power. One method to reduce the volume of the powering unit is to minimize the power supply voltage of the entire system. On the other hand, with the development of the deep sub-micron CMOS technologies, the minimum channel length for a single transistor has been scaled down aggressively which facilitates the reduction of the chip area as well. Unfortunately, as an inevitable part of analytic systems, analog circuits such as …

Proceedings Of International Conference On Power System Operation And Energy Management, Prof.Srikanta Patnaik Mentor

Conference Proceedings - Full Volumes

In spite of so many advancements in the power and energy sector over the last two decades, its survival to cater quality power with due consideration for planning, coordination, marketing, safety, stability, optimality and reliability is still believed to remain critical. Though it appears simple from the outside, yet the internal structure of large scale power systems is so complex that event management and decision making requires a formidable preliminary preparation, which gets still worsened in the presence of uncertainties and contingencies. These aspects have attracted several researchers to carryout continued research in this field and their valued contributions have …

Modeling And Simulation Of Z-Source Inverter, Suresh L

suresh L

Z – source inverters have been recently proposed as an alternative power conversion concept as they have both voltage buck and boost capabilities. These inverters use a unique impedance network, coupled between the power source and converter circuit, to provide both voltage buck and boost properties, which cannot be achieved with conventional voltage source and current source inverters. To facilitate understanding of Z – source inverter, this paper presents a detailed analysis, showing design of impedance network, implementation of simple Boost control PWM technique and simulation of Z – source inverter for different values of modulation indices.

Towards Logic Functions As The Device Using Spin Wave Functions Nanofabric, Prasad Shabadi

Masters Theses 1911 - February 2014

As CMOS technology scaling is fast approaching its fundamental limits, several new nano-electronic devices have been proposed as possible alternatives to MOSFETs. Research on emerging devices mainly focusses on improving the intrinsic characteristics of these single devices keeping the overall integration approach fairly conventional. However, due to high logic complexity and wiring requirements, the overall system-level power, performance and area do not scale proportional to that of individual devices.

Thereby, we propose a fundamental shift in mindset, to make the devices themselves more functional than simple switches. Our goal in this thesis is to develop a new nanoscale fabric paradigm …

A Theoretical Approach To Fault Analysis And Mitigation In Nanoscale Fabrics, Md Muwyid Uzzaman Khan

Masters Theses 1911 - February 2014

High defect rates are associated with novel nanodevice-based systems owing to unconventional and self-assembly based manufacturing processes. Furthermore, in emerging nanosystems, fault mechanisms and distributions may be very different from CMOS due to unique physical layer aspects, and emerging circuit and logic styles. Thus, theoretical fault models for nanosystems are necessary to extract detailed characteristics of fault generation and propagation. Using the intuition garnered from the theoretical analysis, modular and structural redundancy schemes can be specifically tailored to the intricacies of the fabric in order to achieve higher reliability of output signals.

In this thesis, we develop a detailed analytical …

Secure And Energy Efficient Physical Unclonable Functions, Sudheendra Srivathsa

Masters Theses 1911 - February 2014

Physical Unclonable Functions are a unique class of circuits that leverage the inherentvariations in manufacturing process to create unique,unclonableIDs and secret keys.The distinguishing feature of PUFs is that even an untrusted foundry cannot create a copy of the circuit as it is impossible to control the manufacturing process variations.PUFs can operate reliably in presence of voltage and temperature variations. In thisthesis, weexplorethe security offered by PUFs and tradeoffs between different metrics such as uniqueness, reliability and energy consumption.Benefits of sub-threshold PUF operation and the use of delay based Arbiter PUFs and ring oscillator PUFs in low power applications is evaluated. …

A Study Of The Impact Of Computational Delays In Missile Interception Systems, Ye Xu

Masters Theses 1911 - February 2014

Most publications discussing missile interception systems assume a zero computer response time. This thesis studies the impact of computer response time on single-missile single-target and multiple- missile multiple-target systems. Simulation results for the final miss distance as the computer response time increases are presented. A simple online cooperative adjustment model for multiple-missile multiple-target system is created for the purpose of studying the computer delay effect.

Critical Area Driven Dummy Fill Insertion To Improve Manufacturing Yield, Nishant Dhumane

Masters Theses 1911 - February 2014

Non-planar surface may cause incorrect transfer of patterns during lithography. In today’s IC manufacturing, chemical mechanical polishing (CMP) is used for topographical planarization. Since polish rates for metals and oxides are different, dummy metal fills in layout is used to minimize post-CMP thickness variability. Traditional metal fill solutions focus on satisfying density target determined by layout density analysis techniques. These solutions may potentially reduce yield by increasing probability of failure (POF) due to particulate defects and also impact design performance. Layout design solutions that minimize POF and also improve surface planarity via dummy fill insertions have competing requirements for line …

N3asics: Designing Nanofabrics With Fine-Grained Cmos Integration, Pavan Panchapakeshan

Masters Theses 1911 - February 2014

Nanoscale-computing fabrics based on novel materials such as semiconductor nanowires, carbon nanotubes, graphene, etc. have been proposed in recent years. These fabrics employ unconventional manufacturing techniques like Nano-imprint lithography or Super-lattice Nanowire Pattern Transfer to produce ultra-dense nano-structures. However, one key challenge that has received limited attention is the interfacing of unconventional/self-assembly based approaches with conventional CMOS manufacturing to build integrated systems.

We propose a novel nanofabric approach that mixes unconventional nanomanufacturing with CMOS manufacturing flow and design rules to build a reliable nanowire-CMOS 3-D integrated fabric called N³ASICs with no new manufacturing constraints. In N³ASICs …

Universal Computer Aided Design For Electrical Machines, Aravind Cv, Grace I, Rozita Teymourzadeh, Rajkumar R, Raj R, Wong Yv

Dr. Rozita Teymourzadeh, CEng.

Modeling All Spin Logic: Multi-Magnet Networks Interacting Via Spin Currents, Srikant Srinivasan

Srikant Srinivasan

All-spin logic (ASL) represents a new approach to information processing where the roles of charges and capacitors in CMOS are played by spins and magnets. This paper (1) summarizes our earlier work on the input-output isolation and intrinsic directivity of ASL devices, (2) uses an experimentally benchmarked simulator for multimagnet networks coupled by spin transport channels to demonstrate a combinational NAND gate, and (3) describes the natural mapping of such ASL networks into neuromorphic circuits suitable for hybrid analog/digital information processing.

An Rf Cmos Implementation Of An Adaptive Filter For Narrow-Band Interferer Suppression In Uwb Systems, Markus Both

Theses, Dissertations, and Student Research from Electrical & Computer Engineering

Ultra-wideband (UWB) technology is a new type of technology for wireless communication that is based on the transmission of low power sub-nanosecond pulses. UWB communication utilizes a large bandwidth that overlaps and is coexistent with other wireless communication standards that can be also considered as narrow-band interferers. Because UWB systems are highly susceptible to narrow-band interferers, there is a demand for interferer suppression. An adaptive filter consisting of a two-element diversity receiver that performs minimum mean square error combining (MMSE) by the LMS algorithm is proposed. Thereby the elements of the LMS algorithm as well as the receiver LNA were …

A 2-D Processor Array For Massively Parallel Image Processing, Anantha Krishna Nelliparthi

Theses, Dissertations, and Student Research from Electrical & Computer Engineering

The concept of introducing image processing logic within the spatial gaps of an array of photodiodes is the key factor behind the presented work. A two-dimensional massively parallel image processing paradigm based on 8X8 pixel neighborhood digital processors has been designed. A low complexity processor array architecture along with its instruction set has been designed and fully verified on a FPGA platform. Various image processing tests have been run on the FPGA platform to demonstrate the functionality of a design that uses 12 parallel processors. The test results indicate that the architecture is scalable to support high frame rates while …