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Nanotechnology Fabrication

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Articles 181 - 202 of 202

Full-Text Articles in Electronic Devices and Semiconductor Manufacturing

Enhanced Light Extraction Efficiency From Gan Light Emitting Diodes Using Photonic Crystal Grating Structures, Simeon S. Trieu Jun 2010

Enhanced Light Extraction Efficiency From Gan Light Emitting Diodes Using Photonic Crystal Grating Structures, Simeon S. Trieu

Master's Theses

Gallium nitride (GaN) light emitting diodes (LED) embody a large field of research that aims to replace inefficient, conventional light sources with LEDs that have lower power, higher luminosity, and longer lifetime. This thesis presents an international collaboration effort between the State Key Laboratory for Mesoscopic Physics in Peking University (PKU) of Beijing, China and the Electrical Engineering Department of California Polytechnic State University, San Luis Obispo. Over the course of 2 years, Cal Poly’s side has simulated GaN LEDs within the pure blue wavelength spectrum (460nm), focusing specifically on the effects of reflection gratings, transmission gratings, top and bottom …

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Theory Of ‘Selectivity’ Of Label-Free Nanobiosensors – A Geometro-Physical Perspective, Pradeep R. Nair, Muhammad A. Alam Jan 2010

Theory Of ‘Selectivity’ Of Label-Free Nanobiosensors – A Geometro-Physical Perspective, Pradeep R. Nair, Muhammad A. Alam

Birck and NCN Publications

Modern label-free biosensors are generally far more sensitive and require orders of magnitude less incubation time compared to their classical counterparts. However, a more important characteristic regarding the viability of this technology for applications in Genomics/Proteomics is defined by the ‘Selectivity’, i.e., the ability to concurrently and uniquely detect multiple target biomolecules in the presence of interfering species. Currently, there is no theory of Selectivity that allows optimization of competing factors and there are few experiments to probe this problem systematically. In this article, we use the elementary considerations of surface exclusion, diffusion limited transport, and void distribution function to …

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Super-High-Frequency Two-Port Aln Contour-Mode Resonators For Rf Applications, Matteo Rinaldi, Chiara Zuniga, Chengjie Zuo, Gianluca Piazza Dec 2009

Super-High-Frequency Two-Port Aln Contour-Mode Resonators For Rf Applications, Matteo Rinaldi, Chiara Zuniga, Chengjie Zuo, Gianluca Piazza

Matteo Rinaldi

This paper reports on the design and experimental verification of a new class of thin-film (250 nm) super-high-frequency laterally-vibrating piezoelectric microelectromechanical (MEMS) resonators suitable for the fabrication of narrow-band MEMS filters operating at frequencies above 3 GHz. The device dimensions have been opportunely scaled both in the lateral and vertical dimensions to excite a contour-extensional mode of vibration in nanofeatures of an ultra-thin (250 nm) AlN film. In this first demonstration, 2-port resonators vibrating up to 4.5 GHz have been fabricated on the same die and attained electromechanical coupling, kt2, in excess of 1.5%. These devices are employed to synthesize …

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The Effect Of The Digit Slicing Architecture On The Fft Butterfly, Yazan Samir, Rozita Teymourzadeh Dec 2009

The Effect Of The Digit Slicing Architecture On The Fft Butterfly, Yazan Samir, Rozita Teymourzadeh

Dr. Rozita Teymourzadeh, CEng.

Most communications systems tend to achieve bandwidth, power and cost efficiencies to capable to describe modulation scheme. Hence for signal modulation orthogonal frequency division multiplexing (OFDM) transceiver is introduced to cover communications demand in four generation. However high performance Fast Fourier Transforms (FFT) as a main heart of OFDM acts beyond the view. In order to achieve capable FFT, design and realization of its efficient internal structure is key issues of this research work. In this paper implementation of high performance butterfly for FFT by applying digit slicing technique is presented. The proposed design focused on the trade-off between the …

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Vlsi Implementation Of Novel Class Of High Speed Pipelined Digital Signal Processing Filter For Wireless Receivers, Rozita Teymourzadeh, Yazan Samir, Shabuil Islam, Masuri Othman, Mok Vh Dec 2009

Vlsi Implementation Of Novel Class Of High Speed Pipelined Digital Signal Processing Filter For Wireless Receivers, Rozita Teymourzadeh, Yazan Samir, Shabuil Islam, Masuri Othman, Mok Vh

Dr. Rozita Teymourzadeh, CEng.

The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation …

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Design Of Automatic Soil Humidity Control Using Maximum Power Point Tracking Controller, Hoe Ck, Vaithlingam A.C., Rozita Teymourzadeh, Rajkumar R Dec 2009

Design Of Automatic Soil Humidity Control Using Maximum Power Point Tracking Controller, Hoe Ck, Vaithlingam A.C., Rozita Teymourzadeh, Rajkumar R

Dr. Rozita Teymourzadeh, CEng.

The photovoltaic system uses the photovoltaic array as a source of electrical power for the direct conversion of the sun’s radiation to direct current without any environmental hazards. The main purpose of this research is to design of a converter with Maximum Power Point Tracker (MPPT) algorithm for any typical application of soil humidity control. Using this setup the major energy from the solar panel is used for the control of soil humidity. The design of the converter with MPPT together with the soil humidity control logic is presented in this paper. Experimental testing of the design controller is implemented …

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On-Chip Implementation Of Pipeline Digit-Slicing Multiplier-Less Butterfly For Fast Fourier Transform Architecture, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam, Mok Vh Dec 2009

On-Chip Implementation Of Pipeline Digit-Slicing Multiplier-Less Butterfly For Fast Fourier Transform Architecture, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam, Mok Vh

Dr. Rozita Teymourzadeh, CEng.

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This study presents on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly, digit-slicing multiplier-less single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT) FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was …

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On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm, Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman Dec 2009

On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm, Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

Fast Fourier transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence Efficient FFT algorithm is always considered. This paper proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating-point Arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently, synthesis report …

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Dna-Decorated Carbon Nanotubes As Sensitive Layer For Aln Contour-Mode Resonant-Mems Gravimetric Sensor, Chiara Zuniga, Matteo Rinaldi, Samuel M. Khamis, Timothy S. Jones, A T. Johnson, Gianluca Piazza Jun 2009

Dna-Decorated Carbon Nanotubes As Sensitive Layer For Aln Contour-Mode Resonant-Mems Gravimetric Sensor, Chiara Zuniga, Matteo Rinaldi, Samuel M. Khamis, Timothy S. Jones, A T. Johnson, Gianluca Piazza

Matteo Rinaldi

In this work a nano-enabled gravimetric chemical sensor prototype based on single-stranded DNA (ss-DNA) decorated single-walled carbon nanotubes (SWNT) as nano-functionalization layer for Aluminun Nitride (AIN) contour-mode resonant-MEMS gravimetric sensors has been demonstrated. Two resonators fabricated on the same silicon chip and operating at different resonance frequencies, 287 and 450 MHz, were functionalized with this novel bio-coating layer to experimentally prove the capability of two distinct single strands of DNA bound to SWNT to enhance differently the adsorption of volatile organic compounds such as dinitroluene (DNT, simulant for explosive vapor) and dymethyl-methylphosphonate (DMMP, a simulant for nerve agent sarin). The …

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Nanoenabled Microelectromechanical Sensor For Volatile Organic Chemical Detection, Chiara Zuniga, Matteo Rinaldi, Samuel M. Khamis, A. T. Johnson, Gianluca Piazza Jun 2009

Nanoenabled Microelectromechanical Sensor For Volatile Organic Chemical Detection, Chiara Zuniga, Matteo Rinaldi, Samuel M. Khamis, A. T. Johnson, Gianluca Piazza

Matteo Rinaldi

A nanoenabled gravimetric chemical sensor prototype based on the large scale integration of single-stranded DNA (ss-DNA) decorated single-walled carbon nanotubes (SWNTs) as nanofunctionalization layer for aluminum nitride contour-mode resonant microelectromechanical (MEM) gravimetric sensors has been demonstrated. The capability of two distinct single strands of DNA bound to SWNTs to enhance differently the adsorption of volatile organic compounds such as dinitroluene (simulant for explosive vapor) and dymethyl-methylphosphonate (simulant for nerve agent sarin) has been verified experimentally. Different levels of sensitivity (17.3 and 28 KHz µm^2/fg) due to separate frequencies of operation (287 and 450 MHz) on the same die have also …

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5-10 Ghz Aln Contour-Mode Nanoelectromechanical Resonators, Matteo Rinaldi, Chiara Zuniga, Gianluca Piazza Jun 2009

5-10 Ghz Aln Contour-Mode Nanoelectromechanical Resonators, Matteo Rinaldi, Chiara Zuniga, Gianluca Piazza

Matteo Rinaldi

This paper reports on the design and experimental verification of Super High Frequency (SHF) laterally vibrating NanoElctroMechanical (NEMS) resonators. For the first time, AlN piezoelectric nanoresonators with multiple frequencies of operation ranging between 5 and 10 GHz have been fabricated on the same chip and attained the highest f-Q product (4.6E12 Hz) ever reported in AlN contour-mode devices. These piezoelectric NEMS resonators are the first of their class to demonstrate on-chip sensing and actuation of nanostructures without the need of cumbersome or power consuming excitation and readout systems. Effective piezoelectric activity has been demonstrated in thin AlN films having vertical …

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Vlsi Implementation Of High Resolution High Speed Low Latency Pipeline Floating Point Adder/Subtractor For Fft Applications, Rozita Teymourzadeh, Burhan Yeop Majlis, Mok Vh, Masuri Othman Dec 2008

Vlsi Implementation Of High Resolution High Speed Low Latency Pipeline Floating Point Adder/Subtractor For Fft Applications, Rozita Teymourzadeh, Burhan Yeop Majlis, Mok Vh, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

This paper presents on-chip implementation of high speed low latency floating point adder /subtractor with high accuracy performance for FFT in OFDM transceiver. However due to high performance and high resolution, the floating point adder is matched with power network applications as well. The design was implemented for 32-bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating -point Arithmetic. The design is focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and …

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Valley Splitting In Si Quantum Dots Embedded In Sige, Srikant Srinivasan Sep 2008

Valley Splitting In Si Quantum Dots Embedded In Sige, Srikant Srinivasan

Srikant Srinivasan

We examine energy spectra of Si quantum dots embedded in Si0.75Ge0.25 buffers using atomistic numerical calculations for dimensions relevant to qubit implementations. The valley degeneracy of the lowest orbital state is lifted and valley splitting fluctuates with monolayer frequency as a function of the dot thickness. For dot thicknesses ≤ 6 nm, valley splitting is found to be >150 μeV. Using the unique advantage of atomistic calculations, we analyze the effect of buffer disorder on valley splitting. Disorder in the buffer leads to the suppression of valley splitting by a factor of 2.5; the splitting fluctuates with ≈ 20 μeV …

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An Ultrahigh Vacuum Complementary Metal Oxide Silicon Compatible Nonlithographic System To Fabricate Nanoparticle-Based Devices, Arghya Banerjee, Biswajit Das Mar 2008

An Ultrahigh Vacuum Complementary Metal Oxide Silicon Compatible Nonlithographic System To Fabricate Nanoparticle-Based Devices, Arghya Banerjee, Biswajit Das

Electrical & Computer Engineering Faculty Research

Nanoparticles of metals and semiconductors are promising for the implementation of a variety of photonic and electronic devices with superior performances and new functionalities. However, their successful implementation has been limited due to the lack of appropriate fabrication processes that are suitable for volume manufacturing. The current techniques for the fabrication of nanoparticles either are solution based, thus requiring complex surface passivation, or have severe constraints over the choice of particle size and material. We have developed an ultrahigh vacuum system for the implementation of a complex nanosystem that is flexible and compatible with the silicon integrated circuit process, thus …

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On-Chip Implementation Of High Speed And High Resolution Pipeline Radix 2 Fft Algorithm, Rozita Teymourzadeh, Masuri Othman Dec 2006

On-Chip Implementation Of High Speed And High Resolution Pipeline Radix 2 Fft Algorithm, Rozita Teymourzadeh, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

A new on-chip implementation of Fast Fourier Transform (FFT) based on Radix 2 is presented. The pipeline and parallel approaches are combined to introduce a new high speed FFT algorithm which increases resolution by using floating point calculations in its structures. The design has the merits of low complexity and high speed performance. Furthermore, latency reduction is an important issue to implement the high speed FFT on FPGA. The proposed FFT algorithm shows the latency of (N/2 log(2) N) + 11. Moreover, this algorithm has the advantage of low mean squared error (MSE) of 0.0001 which is preferable to Radix …

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Vlsi Implementation Of High Speed And High Resolution Fft Algorithm Based On Radix 2 For Dsp Application, Nooshin Mahdavi, Rozita Teymourzadeh, Masuri Othman Dec 2006

Vlsi Implementation Of High Speed And High Resolution Fft Algorithm Based On Radix 2 For Dsp Application, Nooshin Mahdavi, Rozita Teymourzadeh, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

Using Fast Fourier Transform (FFT) is indispensable in most signal processing applications. Designing an appropriate algorithm for the implementation of FFT can be efficacious in digital signal processing. Sophisticated techniques such as pipelining and parallel calculations have potential impacts on VLSI implementation of FFT algorithm. Furthermore, a mathematic approach such as floating point calculation achieves higher precision. In this paper, an efficient algorithm with using parallel and pipelining methods is proposed to implement high speed and high resolution FFT algorithm. Latency reduction is an important issue to implement the high speed FFT on FPGA. The Proposed FFT algorithm shows the …

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An Enhancement Of Decimation Process Using Fast Cascaded Integrator Comb (Cic), Rozita Teymourzadeh, Masuri Othman Dec 2005

An Enhancement Of Decimation Process Using Fast Cascaded Integrator Comb (Cic), Rozita Teymourzadeh, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

The over sampling technique has been shown to increase the SNR and is used in many high performance system such as in the ADC for audio and DAT systems. This paper presents the design of the decimation and its VLSI implementation which is the sub-component in the over sampling technique. The design of three main units in the decimation stage that is the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also described. The Verilog HDL code in Xilinx ISE environment has been derived to describe the CIC filter properties and downloaded in …

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An Overview Of The Decimation Process And Its Vlsi Implementation, Rozita Teymourzadeh, Masuri Othman Dec 2005

An Overview Of The Decimation Process And Its Vlsi Implementation, Rozita Teymourzadeh, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

Digital Decimation process plays an important task in communication system. It mostly is applied in transceiver when the frequency reduction is required. However, the decimation process for sigma delta modulator is considered in this research work. The proposed design was simulated using MATLAB software and implemented by hardware description language in Xilinx environment. Furthermore, the proposed advance arithmetic unit is applied to improve the system efficiency.

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An Improved Recursive And Non-Recursive Comb Filter For Dsp Applications, Rozita Teymourzadeh, Masuri Othman Dec 2005

An Improved Recursive And Non-Recursive Comb Filter For Dsp Applications, Rozita Teymourzadeh, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

The recursive and non-recursive comb filters are commonly used as decimators for the sigma delta modulators. This paper presents the analysis and design of low power and high speed comb filters. The comparison is made between the recursive and the non-recursive comb filters with the focus on high speed and saving power consumption. Design procedures and examples are given by using Matlab and Verilog HDL for both recursive and non-recursive comb filter with emphasis on frequency response, transfer function and register width. The implementation results show that non-recursive comb filter has capability of speeding up the circuit and reducing power …

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Vlsi Implementation Of Cascaded Integrator Comb Filters For Dsp Applications, Rozita Teymourzadeh, Masuri Othman Dec 2005

Vlsi Implementation Of Cascaded Integrator Comb Filters For Dsp Applications, Rozita Teymourzadeh, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

The recursive comb filters or Cascaded Integrator Comb filter (CIC) are commonly used as decimators for the sigma delta modulators. This paper presents the VLSI implementation, analysis and design of high speed CIC filters which are based on a low-pass filter. These filters are used in the signal decimation which has the effect on reducing the sampling rate. It is also chosen because its attractive property of both low power and low complexity since it dose not required a multiplier. Simulink toolbox available in Matlab software which is used to simulator and Verilog HDL coding help to verify the functionality …

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On-Chip Implementation Of Cascaded Integrated Comb Filters (Cic) For Dsp Application, Rozita Teymourzadeh, Masuri Othman Dec 2004

On-Chip Implementation Of Cascaded Integrated Comb Filters (Cic) For Dsp Application, Rozita Teymourzadeh, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

This paper presents the design of a CIC filters based on a low-pass filter for reducing the sampling rate, also known as decimation process. The targeted application for the filter is in the analog to digital conversion (ADC).The CIC is chosen because of its attractive property of both low power and complexity since it dose not required multipliers. Simulink toolbox available in Matlab software is used to design and simulate the functionality of the CIC filter. This paper also shows how sample frequency is decreased by CIC filter and it can be used to give enough stop-band attenuation to prevent …

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Investigation Of Nanoporous Thin-Film Alumina Templates, Biswajit Das May 2004

Investigation Of Nanoporous Thin-Film Alumina Templates, Biswajit Das

Electrical & Computer Engineering Faculty Research

This paper presents the results of a systematic study of the fabrication of thin-film alumina templates on silicon and other substrates. Such templates are of significant interest for the low-cost implementation of semiconductor and metal nanostructure arrays. In addition, thin-film alumina templates on silicon have the potential for nanostructure integration with silicon electronics. Formation of thin-film alumina templates on silicon substrates was investigated under different fabrication conditions, and the dependence of pore morphology and pore formation rate on process parameters was evaluated. In addition, process conditions for improved pore size distribution and periodicity were determined. The template/silicon interface, important for …

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