VLSI and Circuits, Embedded and Hardware Systems Commons^™

Bibliometric Review Of Fpga Based Implementation Of Cnn, Priti Shahane, Piyush Tyagi, Purba Saha, Shravan Sainath, Swanand Bedekar

Library Philosophy and Practice (e-journal)

Nowadays Convolution Neural Network (CNN) has become the state of the art for machine learning algorithms due to their high accuracy. However, implementation of CNN algorithms on hardware platforms becomes challenging due to high computation complexity, memory bandwidth and power consumption. Hardware accelerators such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC) are suitable platforms to model CNN algorithms. Recently FPGAs have been considered as an attractive platform for CNN implementation. Modern FPGAs have various embedded hardware and software blocks such as a soft processor, DSP slice and memory blocks. These embedded resources …

Cmos Radioactive Isotope Identification With Multichannel Analyzer And Embedded Neural Network, Samuel Murray

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

A radiation detection and identification system is designed and implemented to perform gamma ray spectroscopy on radioactive sources and identify which isotopes are present in the sources. A multichannel analyzer is implemented on an ASIC to process the signal produced from gamma rays detected by a scintillator and photomultiplier tube and to quantize the gamma ray energies to build a histogram. A fast, low memory embedded neural network is implemented on a microcontroller ASIC to identify the isotopes present in the gamma ray histogram produced by the multichannel analyzer in real time.

Advisors: Sina Balkir and Michael Hoffman

Cmos Smart Camera With Focal Plane Neighborhood-Parallel Image Processing, Joseph A. Schmitz

Department of Electrical and Computer Engineering: Dissertations, Theses, and Student Research

A neighbhorhood-based smart camera architecture is designed and implemented in a 0.13 μm CMOS technology. Each 8 × 8 region of pixels contains a small processor with local memory, which are tiled to form a full-resolution camera. Each processor operates in parallel, enabling high-speed image processing suitable for tracking and recognition tasks. The architecture features the programming flexibility of designs us- ing chip-level and row-level processors while preserving the scalability of pixel-parallel processing elements. The neighborhood processors are implemented physically be- tween the pixel photodiodes, creating multiple design challenges that are discussed in detail.

Advisors: Sina Balkir and Michael Hoffman