Nanotechnology Fabrication Commons^™

Skynet: Memristor-Based 3d Ic For Artificial Neural Networks, Sachin Bhat

Masters Theses

Hardware implementations of artificial neural networks (ANNs) have become feasible due to the advent of persistent 2-terminal devices such as memristor, phase change memory, MTJs, etc. Hybrid memristor crossbar/CMOS systems have been studied extensively and demonstrated experimentally. In these circuits, memristors located at each cross point in a crossbar are, however, stacked on top of CMOS circuits using back end of line processing (BOEL), limiting scaling. Each neuron’s functionality is spread across layers of CMOS and memristor crossbar and thus cannot support the required connectivity to implement large-scale multi-layered ANNs.

This work proposes a new fine-grained 3D integrated circuit technology …

Virtual-Source Based Accurate Model For Predicting Noise Behavior At High Frequencies In Nanoscale Pmos Soi Transistors, Vaibhav R. Ramachandran, Saeed Mohammadi, Sutton Hathorn

The Summer Undergraduate Research Fellowship (SURF) Symposium

Complementary Metal Oxide Semiconductor (CMOS) technology at the nanometre scale is an excellent platform to implement monolithically integratedsystems because of the low cost of manufacturing and ease of integration. Newly developed CMOS Silicon on Insulator (SOI) transistors that are currentlydeveloped are suitable for use in radio frequency circuits. They find applications in many areas such as 5G telecommunication systems, high speed Wi-Fi andairport body-scanners. Unfortunately, the models for CMOS SOI transistors that are currently used in these circuits are inaccurate because of their complexity.The models currently used require the optimization of more than 200 variables. This paper aims to accurately …

Design Automation For Carbon Nanotube Circuits Considering Performance And Security Optimization, Lin Liu

Dissertations, Master's Theses and Master's Reports

As prevailing copper interconnect technology advances to its fundamental physical limit, interconnect delay due to ever-increasing wire resistivity has greatly limited the circuit miniaturization. Carbon nanotube (CNT) interconnects have emerged as promising replacement materials for copper interconnects due to their superior conductivity. Buffer insertion for CNT interconnects is capable of improving circuit timing of signal nets with limited buffer deployment. However, due to the imperfection of fabricating long straight CNT, there exist significant unidimensional-spatially correlated variations on the critical CNT geometric parameters such as the diameter and density, which will affect the circuit performance.

This dissertation develops a novel timing …