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Full-Text Articles in Digital Circuits

Improve The Prototype Of Low-Cost Near-Infrared Diffuse Optical Imaging System, Chen Xu, Mohammed Z. Shakil Dec 2020

Improve The Prototype Of Low-Cost Near-Infrared Diffuse Optical Imaging System, Chen Xu, Mohammed Z. Shakil

Publications and Research

Diffuse Optical Tomography (DOT) and Optical Spectroscopy using near-infrared (NIR) diffused light has demonstrated great potential for the initial diagnosis of tumors and in the assessment of tumor vasculature response to neoadjuvant chemotherapy. The aims of this project are 1) to test the different types of LEDs in the near-infrared range, and design the driving circuit, and test the modulation of LEDs at different frequencies; 2) to test the APDs as a detector, and build the receiver system and compare efficiency with pre-built systems. In this project, we are focusing on creating a low-cost infrared transmission system for tumor and …


Otter Vector Extension, Alexis A. Peralta Jun 2020

Otter Vector Extension, Alexis A. Peralta

Computer Engineering

This paper offers an implementation of a subset of the "RISC-V 'V' Vector Extension", v0.7.x. The "RISC-V 'V' Vector Extension" is the proposed vector instruction set for RISC-V open-source architecture. Vectors are inherently data-parallel, allowing for significant performance increases. Vectors have applications in fields such as cryptography, graphics, and machine learning. A vector processing unit was added to Cal Poly's RISC-V multi-cycle architecture, known as the OTTER. Computationally intensive programs running on the OTTER Vector Extension ran over three times faster when compared to the baseline multi-cycle implementation. Memory intensive applications saw similar performance increases.


Otter Debugger, Keefe Johnson Jun 2020

Otter Debugger, Keefe Johnson

Computer Engineering

This project is a debugger and programmer for the OTTER CPU, the implementation of the RISC-V ISA used by Cal Poly to teach computer architecture and assembly language in CPE 233/333 and usually implemented on the Basys3 FPGA development board. With this tool, students can quickly program their OTTER with a new/revised RISC-V program binary without resynthesizing the entire FPGA design. They can then use the debugger from a PC to pause/continue/single-step execution and set breakpoints, while inspecting and modifying register and memory contents. This enables real-time debugging of OTTER projects involving custom hardware such as a keyboard and VGA …


Nonlinear Least Squares 3-D Geolocation Solutions Using Time Differences Of Arrival, Michael V. Bredemann Apr 2020

Nonlinear Least Squares 3-D Geolocation Solutions Using Time Differences Of Arrival, Michael V. Bredemann

Mathematics & Statistics ETDs

This thesis uses a geometric approach to derive and solve nonlinear least squares minimization problems to geolocate a signal source in three dimensions using time differences of arrival at multiple sensor locations. There is no restriction on the maximum number of sensors used. Residual errors reach the numerical limits of machine precision. Symmetric sensor orientations are found that prevent closed form solutions of source locations lying within the null space. Maximum uncertainties in relative sensor positions and time difference of arrivals, required to locate a source within a maximum specified error, are found from these results. Examples illustrate potential requirements …


Annual Report 2019-2020, Depaul University College Of Computing And Digital Media Jan 2020

Annual Report 2019-2020, Depaul University College Of Computing And Digital Media

CDM Annual Reports

LETTER FROM THE DEAN

As I write this letter wrapping up the 2019-20 academic year, we remain in a global pandemic that has profoundly altered our lives. While many things have changed, some stayed the same: our CDM community worked hard, showed up for one another, and continued to advance their respective fields. A year that began like many others changed swiftly on March 11th when the University announced that spring classes would run remotely. By March 28th, the first day of spring quarter, we had moved 500 CDM courses online thanks to the diligent work of our faculty, staff, …


Systematic Model-Based Design Assurance And Property-Based Fault Injection For Safety Critical Digital Systems, Athira Varma Jayakumar Jan 2020

Systematic Model-Based Design Assurance And Property-Based Fault Injection For Safety Critical Digital Systems, Athira Varma Jayakumar

Theses and Dissertations

With advances in sensing, wireless communications, computing, control, and automation technologies, we are witnessing the rapid uptake of Cyber-Physical Systems across many applications including connected vehicles, healthcare, energy, manufacturing, smart homes etc. Many of these applications are safety-critical in nature and they depend on the correct and safe execution of software and hardware that are intrinsically subject to faults. These faults can be design faults (Software Faults, Specification faults, etc.) or physically occurring faults (hardware failures, Single-event-upsets, etc.). Both types of faults must be addressed during the design and development of these critical systems. Several safety-critical industries have widely adopted …


Recipe For Disaster, Zac Travis Mar 2019

Recipe For Disaster, Zac Travis

MFA Thesis Exhibit Catalogs

Today’s rapid advances in algorithmic processes are creating and generating predictions through common applications, including speech recognition, natural language (text) generation, search engine prediction, social media personalization, and product recommendations. These algorithmic processes rapidly sort through streams of computational calculations and personal digital footprints to predict, make decisions, translate, and attempt to mimic human cognitive function as closely as possible. This is known as machine learning.

The project Recipe for Disaster was developed by exploring automation in technology, specifically through the use of machine learning and recurrent neural networks. These algorithmic models feed on large amounts of data as a …


Annual Report 2018-2019, Depaul University College Of Computing And Digital Media Jan 2019

Annual Report 2018-2019, Depaul University College Of Computing And Digital Media

CDM Annual Reports

LETTER FROM THE DEAN

I am pleased to share with you the 2018-19 College of Computing and Digital Media (CDM) annual report, highlighting the important work done by our faculty, students, and staff. We’ve said this before, and we’ll say it again: it was a big year. In 2018-19, programs across all three of our schools (Computing, Cinematic Arts, and Design) were ranked nationally. Our faculty were published in dozens of scholarly journals, screened their films over 100 times, and had their work exhibited globally. Student and alumni accomplishments included an Emmy nomination, a first place win in a Department …


Investigating On Through Glass Via Based Rf Passives For 3-D Integration, Libo Qian, Jifei Sang, Yinshui Xia, Jian Wang, Peiyi Zhao Jun 2018

Investigating On Through Glass Via Based Rf Passives For 3-D Integration, Libo Qian, Jifei Sang, Yinshui Xia, Jian Wang, Peiyi Zhao

Mathematics, Physics, and Computer Science Faculty Articles and Research

Due to low dielectric loss and low cost, glass is developed as a promising material for advanced interposers in 2.5-D and 3-D integration. In this paper, through glass vias (TGVs) are used to implement inductors for minimal footprint and large quality factor. Based on the proposed physical structure, the impact of various process and design parameters on the electrical characteristics of TGV inductors is investigated with 3-D electromagnetic simulator HFSS. It is observed that TGV inductors have identical inductance and larger quality factor in comparison with their through silicon via counterparts. Using TGV inductors and parallel plate capacitors, a compact …


Arm Mke1xf Mcu Replatform, Nathan Hong, Derek Lung, Japsimran Singh, Bevin Tang Jun 2018

Arm Mke1xf Mcu Replatform, Nathan Hong, Derek Lung, Japsimran Singh, Bevin Tang

Computer Engineering

After Cal Poly Racing’s electrical team began to hit the technical limits of the ADC and other I/O features of the current 8-bit Atmel AT90 microcontroller unit, it became clear that an upgrade was due. This replatforming project takes the functionalities of the old, 8-bit architecture, and aims to provide a 32-bit version using the ARM MKE1xF MCU. With the idea of having a working PCB as a stretch goal, the scope of the library development was limited to enable base functionality. Thus, the only libraries developed were for the Timer, ADC, SPI, UART, and CAN. Additionally, this document discusses …


A Basic, Four Logic Cluster, Disjoint Switch Connected Fpga Architecture, Joseph Prachar Jun 2018

A Basic, Four Logic Cluster, Disjoint Switch Connected Fpga Architecture, Joseph Prachar

Computer Engineering

This paper seeks to describe the process of developing a new FPGA architecture from nothing, both in terms of knowledge about FPGAs and in initial design material. Specifically, this project set out to design an FPGA architecture which can implement a simple state machine type design with 10 inputs, 10 outputs and 10 states. The open source Verilog-to-Routing FPGA CAD flow tool was used in order to synthesize, place, and route HDL files onto the architecture. This project was completed in terms of the spirit of the original goals of implementing an FPGA from scratch. Although, the project resulted in …


Automating Knife-Edge Method Of Thz Beam Characterization, Christopher Charles Faber May 2018

Automating Knife-Edge Method Of Thz Beam Characterization, Christopher Charles Faber

Maseeh Summer Undergraduate Research Experience

The goal of this project is to create a time and cost-effective solution for THz beam profiling.

The knife edge method of beam characterization is a technique to verify the intensity profile of a beam involving traveling a blade orthogonal to the beam path and measuring transmission in successive steps. We use a vector network analyzer (VNA) to measure S21 transmission from a THz source. Manual implementation of this method was time-consuming and inefficient.

Project hardware includes an Arduino, a motor shield, and a ball screw linear rail with stepper motor actuator. Software was created in LabView and data is …


Improving System-On-Chip Test Networks For: Bandwidth, Security, And Power, Saurabh Gupta May 2018

Improving System-On-Chip Test Networks For: Bandwidth, Security, And Power, Saurabh Gupta

Computer Science and Engineering Theses and Dissertations

Modern System-on-Chips (SoCs) provide benefits such as reduction in overall system cost, and size, increased performance, and lower power consumption. Increasing complexity of these Integrated Circuits (ICs) has resulted in a higher probability of manufacturing defects. Manufacturing defects can result in the faulty operation of a system. Thus, it is essential to test an IC after it is manufactured to detect any possible faults in it. These SoCs include on-chip embedded instruments that can be used for test, debug, diagnosis, validation, monitoring, characterization, configuration, or functional purposes. IEEE 1687 Std. (IJTAG) provides a standard interface for the reconfigurable access and …


Annual Report 2017-2018, Depaul University College Of Computing And Digital Media Jan 2018

Annual Report 2017-2018, Depaul University College Of Computing And Digital Media

CDM Annual Reports

LETTER FROM THE DEAN

I am pleased to share with you the College of Computing and Digital Media’s (CDM) 2017-18 annual report, highlighting the many achievements across our community. It was a big year. We began offering five new programs (two bachelor’s, two master’s, and one PhD) across our three schools, in addition to several new certificate programs through our Institute for Professional Development. We built new, cutting-edge spaces to support these and other programs— most notably a 4,500 square-foot makerspace, a robotics and medical engineering lab, an augmented and virtual reality lab, and plans for a cyber-physical systems project …


Toward Biologically-Inspired Self-Healing, Resilient Architectures For Digital Instrumentation And Control Systems And Embedded Devices, Shawkat Sabah Khairullah Jan 2018

Toward Biologically-Inspired Self-Healing, Resilient Architectures For Digital Instrumentation And Control Systems And Embedded Devices, Shawkat Sabah Khairullah

Theses and Dissertations

Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes. One of the more essential concepts for achieving this goal is the notion of resilient and survivable digital I&C systems. In recent years, self-healing concepts based on biological physiology have received attention for the design of robust digital systems. However, many of these approaches have not been architected from the outset with safety in mind, nor have they been targeted for the automation community where a significant need exists. This dissertation presents a new self-healing digital …


Energy And Performance Balancing Architecture For Asynchronous Data Processing Platforms, Chien-Wei Lo Aug 2017

Energy And Performance Balancing Architecture For Asynchronous Data Processing Platforms, Chien-Wei Lo

Graduate Theses and Dissertations

The semiconductor industry has been increasingly focused on the energy consumption and heat generation in CMOS-based integrated circuits (ICs) for its dominating impact on the system performance and reliability. Without clock-related timing constraints, asynchronous circuits have demonstrated unique flexibility in performance-energy tradeoffs compared to synchronous designs. This dissertation work presents the architecture capable of balancing energy and performance for asynchronous digital signal processing circuits using the Multi-Threshold NULL Convention Logic (MTNCL). Architecture implementing user-configurable adaptive dynamic voltage scaling (DVS) and data processing core disabling based on the detection and parameterization of system throughput are developed for MTNCL parallel homogeneous and …


One-To-Cloud One-Time Pad Data Encryption: Introducing Virtual Prototyping With Pspice, Paul Tobin, Lee Tobin, Roberto Gandia Blanquer Dr, Michael Mckeever, Jonathan Blackledge Jun 2017

One-To-Cloud One-Time Pad Data Encryption: Introducing Virtual Prototyping With Pspice, Paul Tobin, Lee Tobin, Roberto Gandia Blanquer Dr, Michael Mckeever, Jonathan Blackledge

Conference papers

In this paper, we examine the design and application of a one-time pad encryption system for protecting data stored in the Cloud. Personalising security using a one-time pad generator at the client-end protects data from break-ins, side-channel attacks and backdoors in public encryption algorithms. The one-time pad binary sequences were obtained from modified analogue chaos oscillators initiated by noise and encoded client data locally. Specific ``one-to-Cloud'' storage applications returned control back to the end user but without the key distribution problem normally associated with one-time pad encryption. Development of the prototype was aided by ``Virtual Prototyping'' in the latest version …


Solid State Drive, Shaun A. Steele Jun 2017

Solid State Drive, Shaun A. Steele

Electrical Engineering

This project documents the design and implementation of a solid state drive (SSD). SSDs are a non-volatile memory storage device that competes with hard disk drives. SSDs rely on flash memory, a type of non-volatile memory that is electrically erased and programmed. The appeal of SSDs lies in the fact that they allow a fast, reliable, and durable memory storage device. The goal of this project is to have a working external SSD built from scratch.


Power Efficient High Temperature Asynchronous Microcontroller Design, Nathan William Kuhns May 2017

Power Efficient High Temperature Asynchronous Microcontroller Design, Nathan William Kuhns

Graduate Theses and Dissertations

There is an increasing demand for dependable and efficient digital circuitry capable of operating in high temperature environments. Extreme temperatures have adverse effects on traditional silicon synchronous systems because of the changes in delay and setup and hold times caused by the variances in each device’s threshold voltage. This dissertation focuses on the design of the major functionality of an asynchronous 8051 microcontroller in Raytheon’s high temperature Silicon Carbide process, rated for operation over 300ºC. The microcontroller is designed in NULL Convention Logic, for which the traditional bus architecture used for data transfer would consume a large amount of power. …


Sensor Placement With Time-To-Detection Guarantees, Saif Eddin Jabari, Laura Wynter Dec 2016

Sensor Placement With Time-To-Detection Guarantees, Saif Eddin Jabari, Laura Wynter

Research Collection School Of Computing and Information Systems

We present a novel and effective method for determining the placement of sensors so as to be able to satisfy probabilistic constraints on the time-to-detection of an incident. Indeed, with the wealth of real-time traffic data available today, an important new goal of intelligent traffic management systems is incident detection with time-to-detection guarantees, in particular on expressways with large distances between sensors. This goal drives investment decisions in new sensor deployment, hence making the topic a pressing need for traffic management. The method we provide makes use of a probabilistic formulation of traffic behavior and incident localization to determine the …


Pinpoint: Location Beacon And Tracking, Ezequiel Lopez Iii Jun 2016

Pinpoint: Location Beacon And Tracking, Ezequiel Lopez Iii

Computer Engineering

The purpose of Pinpoint was to create a device that can collect and transmit location information for multiple users on a wireless network. The device would be used to keep track of and communicate with other users nearby. The final design includes a touchscreen display as a graphical user interface (GUI), an XBee RF module for wireless networking, a GPS receiver for location tracking, and a Programmable System on a Chip (PSoC) to control the modules.


“My Logic Is Undeniable”: Replicating The Brain For Ideal Artificial Intelligence, Samuel C. Adams Apr 2016

“My Logic Is Undeniable”: Replicating The Brain For Ideal Artificial Intelligence, Samuel C. Adams

Senior Honors Theses

Alan Turing asked if machines can think, but intelligence is more than logic and reason. I ask if a machine can feel pain or joy, have visions and dreams, or paint a masterpiece. The human brain sets the bar high, and despite our progress, artificial intelligence has a long way to go. Studying neurology from a software engineer’s perspective reveals numerous uncanny similarities between the functionality of the brain and that of a computer. If the brain is a biological computer, then it is the embodiment of artificial intelligence beyond anything we have yet achieved, and its architecture is advanced …


Estimation On Gibbs Entropy For An Ensemble, Lekhya Sai Sake Dec 2015

Estimation On Gibbs Entropy For An Ensemble, Lekhya Sai Sake

Electronic Theses, Projects, and Dissertations

In this world of growing technology, any small improvement in the present scenario would create a revolution. One of the popular revolutions in the computer science field is parallel computing. A single parallel execution is not sufficient to see its non-deterministic features, as same execution with the same data at different time would end up with a different path. In order to see how non deterministic a parallel execution can extend up to, creates the need of the ensemble of executions. This project implements a program to estimate the Gibbs Entropy for an ensemble of parallel executions. The goal is …


Forest Sign Maker, Victor Espinosa Iii, Kevin Ly, Lisa Yip Jun 2015

Forest Sign Maker, Victor Espinosa Iii, Kevin Ly, Lisa Yip

Mechanical Engineering

Executive Summary:

The Inyo National Forest is arguably one of the most beautiful locations in California, containing natural masterpieces such as Mount Whitney and the Ancient Bristlecone Pine Forest. Despite its magnificence, the Inyo National Forest can be a treacherous region. The Friends of the Inyo take pride in being able to facilitate the viewing experience for all outdoorsmen by maintaining the mountain trails, which includes providing adequate trail signage.

Unfortunately, there is a fundamental issue with the recent state of trail signage in the Inyo National Forest: the rate at which signs are being vandalized or naturally destroyed is …


Designing A Modular Dsp Core For Real-Time Audio Performance, Kevin Richard Brewer Jun 2014

Designing A Modular Dsp Core For Real-Time Audio Performance, Kevin Richard Brewer

Computer Engineering

This project provides an overview for building a Digital Signal Processing (DSP) core on a Digilent Nexys2 FPGA board. The DSP core is designed to give Cal Poly students interested in DSP and its applications to audio engineering a usable platform to perform signal processing and analytics. The processes of the DSP core are modular, allowing students to design their own implementations of various adder and multiplier functions. Infinite impulse response (IIR) filters and finite impulse response (FIR) filters using both cascade and parallel implementations are the primary processing tools in the core, and all output can be visually and …


Open Cortex-M0™ Modular Debug Unit, Chuan Yean Tan, Matthew Swabey Oct 2013

Open Cortex-M0™ Modular Debug Unit, Chuan Yean Tan, Matthew Swabey

The Summer Undergraduate Research Fellowship (SURF) Symposium

The debug unit of a modern digital system on chip (SoC) is a critical unit that allows users to monitor and analyze the chip’s activity that occurs throughout a SoC design. Selection of the debug unit’s correct feature set and architecture are critical to the success of the design. Debugging systems that exist have different architectures and are closely coupled to their host SoCs. As a consequence they are resource intensive to improve on due to the different nature of each SoC designs. Moreover, the bus protocols that allow the debug unit to interact with the SoC design are often …


Bluemote!, Philip Kaye Mar 2012

Bluemote!, Philip Kaye

Computer Engineering

In today’s society, our mobile phones are an extremely useful device when we are on the go and away from our homes; however, when we return home, our smart phone becomes just a communication tool again. Home automation is inevitable, and it will find its way into every house. The first person to commercialize it to the point where it is as easy to set-up and as affordable as a home router will end up breaking this slow trend. The key to this success is the smart phone; this should end up being the most expensive piece of hardware for …


Full Custom Vlsi Design Of On-Line Stability Checkers, Chris Y. Lee Aug 2011

Full Custom Vlsi Design Of On-Line Stability Checkers, Chris Y. Lee

Master's Theses

A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.

A method for concurrent fault testing called On-line Stability Checking …


Detection Of Breathing And Infant Sleep Apnea, Brian Berg Jun 2011

Detection Of Breathing And Infant Sleep Apnea, Brian Berg

Computer Engineering

Sleep apnea is a condition where people pause while breathing in their sleep; this can be of great concern for infants and premature babies. Current monitoring systems either require physical attachment to a user or may be unreliable. This project is meant to develop a device that can accurately detect breathing through sound and issue appropriate warnings upon its cessation. The device produced is meant to be a standalone device and thus was developed as an embedded systems project on a Xilinx Spartan 6 FPGA.


Project 308: Augmented Reality Mario Kart, Joseph Abad, David Allender, Joryl Calizo, Ryan Gaspar, Gavin Lee Jun 2011

Project 308: Augmented Reality Mario Kart, Joseph Abad, David Allender, Joryl Calizo, Ryan Gaspar, Gavin Lee

Computer Engineering

Mario Kart is a popular go-kart racing game developed by Nintendo. The premise of the game is simple: drive a go-kart along a racetrack and reach the finish line before the other players. What makes this game unique, however, is the inclusion of weapons, traps, and other projectiles that a player can use to gain an advantage in the race. We have taken on the challenge of not only recreating this amazing game, but using the art of Augmented Reality to fully immerse the player in the full experience. Rather than play the game on a television screen with a …