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Articles 61 - 65 of 65
Full-Text Articles in Digital Circuits
Development Of A Cubesat Payload To Model Particle Dampening In Space: Design And Implementation Of Software For Cp7, Daniel Walker
Development Of A Cubesat Payload To Model Particle Dampening In Space: Design And Implementation Of Software For Cp7, Daniel Walker
Computer Engineering
The California Polytechnic State University CubeSat student research & development group, PolySat, is currently in a mature development stage of a single unit CubeSat designated CP7. The CP7 mission implements a scientific payload designed to characterize particle dampers in microgravity conditions. When subjected to vibration, the momentum exchanges and frictional forces of the particles create a damping effect that can be optimized to suit a number of applications over a broad frequency and amplitude range. In space based applications, particle dampers would serve as a robust and simple device to eliminate jitter in optical assemblies and other sensitive instrumentation. This …
Asynchronous Mips Processors: Educational Simulations, Robert L. Webb
Asynchronous Mips Processors: Educational Simulations, Robert L. Webb
Master's Theses
The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …
Performance Evaluation Of A Field Programmable Gate Array-Based System For Detecting And Tracking Peer-To-Peer Protocols On A Gigabit Ethernet Network, Brennon D. Thomas
Performance Evaluation Of A Field Programmable Gate Array-Based System For Detecting And Tracking Peer-To-Peer Protocols On A Gigabit Ethernet Network, Brennon D. Thomas
Theses and Dissertations
Recent years have seen a massive increase in illegal, suspicious, and malicious traffic traversing government and military computer networks. Some examples include illegal file distribution and disclosure of sensitive information using the BitTorrent file sharing protocol, criminals and terrorists using Voice over Internet Protocol (VoIP) technologies to communicate, and foreign entities exfiltrating sensitive data from government, military, and Department of Defense contractor networks. As a result of these growing threats, the TRacking and Analysis for Peer-to-Peer (TRAPP) system was developed in 2008 to detect BitTorrent and VoIP traffic of interest. The TRAPP system, designed on a Xilinx Virtex-II Pro Field …
Pretty Lights, Nicholas (Nick) Delmas, Matthew (Matt) Maniaci
Pretty Lights, Nicholas (Nick) Delmas, Matthew (Matt) Maniaci
Computer Engineering
Digital media players often include a visualization component that allows a user to watch a visualization synchronized to their music or videos. This project uses the visualization plugin API of an existing media playback program (WinAmp) but it displays its visuals using physical LED lights. Instead of outputting visuals to the computer screen, data is sent over USB to a micro controller that runs the LED lights. This project aims to give users a more visceral visual experience than traditional visualizations on the computer screen.
Implementation And Performance Of Error Correction Codes For High-Speed Computer Networks, Jochen Spengler
Implementation And Performance Of Error Correction Codes For High-Speed Computer Networks, Jochen Spengler
Dissertations and Theses
During the transmission of data there is always a possibility that errors occur and some pieces are modified. If the receiver detects an error it either sends a request for retransmission or, like in networks using Ethernet, it does not send an acknowledgment for the erroneous frame. In this case the sender waits a certain time and retransmits the frame. With the development of faster computer networking hardware and the need for more real-time applications, these errors have become a major concern. Long retransmission latencies and the need for large memories for buffering drive the development of more reliable network …