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Articles 121 - 150 of 207
Full-Text Articles in Computer Engineering
A Scalable, Chunk-Based Slicer For Cooperative 3d Printing, Jace J. Mcpherson
A Scalable, Chunk-Based Slicer For Cooperative 3d Printing, Jace J. Mcpherson
Computer Science and Computer Engineering Undergraduate Honors Theses
Cooperative 3D printing is an emerging technology that aims to increase the 3D printing speed and to overcome the size limit of the printable object by having multiple mobile 3D printers (printhead-carrying mobile robots) work together on a single print job on a factory floor. It differs from traditional layer-by-layer 3D printing due to requiring multiple mobile printers to work simultaneously without interfering with each other. Therefore, a new approach for slicing a digital model and generating commands for the mobile printers is needed, which has not been discussed in literature before. We propose a chunk-by-chunk based slicer that divides …
Collaborative Robotic Path Planning For Industrial Spraying Operations On Complex Geometries, Steven Brown
Collaborative Robotic Path Planning For Industrial Spraying Operations On Complex Geometries, Steven Brown
Graduate Theses and Dissertations
Implementation of automated robotic solutions for complex tasks currently faces a few major hurdles. For instance, lack of effective sensing and task variability – especially in high-mix/low-volume processes – creates too much uncertainty to reliably hard-code a robotic work cell. Current collaborative frameworks generally focus on integrating the sensing required for a physically collaborative implementation. While this paradigm has proven effective for mitigating uncertainty by mixing human cognitive function and fine motor skills with robotic strength and repeatability, there are many instances where physical interaction is impractical but human reasoning and task knowledge is still needed. The proposed framework consists …
Efficacy Of Multi-Threshold Null Convention Logic In Low-Power Applications, Brent Bell
Efficacy Of Multi-Threshold Null Convention Logic In Low-Power Applications, Brent Bell
Graduate Theses and Dissertations
In order for an asynchronous design paradigm such as Multi-Threshold NULL Convention Logic (MTNCL) to be adopted by industry, it is important for circuit designers to be aware of its advantages and drawbacks especially with respect to power usage. The power tradeoff between MTNCL and synchronous designs depends on many different factors including design type, circuit size, process node, and pipeline granularity. Each of these design dimensions influences the active power and the leakage power comparisons. This dissertation analyzes the effects of different design dimensions on power consumption and the associated rational for these effects. Results show that while MTNCL …
Designing A Distributed Network Of Air Quality Sensors, Kaylee Rauso
Designing A Distributed Network Of Air Quality Sensors, Kaylee Rauso
Computer Science and Computer Engineering Undergraduate Honors Theses
The deterioration of human and environmental health due to worsening outdoor air quality is a serious global threat. A step towards improving the current state of ambient air worldwide is the increased collection of data for government policy, research, and general public use. Currently, reliable data is only collected at a handful of sites in the state of Arkansas and sparsely across the country. The purpose of this project was to design an inexpensive air quality sensor to saturate entire cities with nodes which transmit air data to a sensor for a web application to display. The prototype node was …
Comparison Of Data Transfer Alternatives In Asynchronous Circuits, Mark Howard
Comparison Of Data Transfer Alternatives In Asynchronous Circuits, Mark Howard
Computer Science and Computer Engineering Undergraduate Honors Theses
Digital integrated circuits (ICs) have become progressively complex in their functionality. This has sped up the demand for asynchronous architectures, which operate without any clocking scheme, considering new challenges in the timing of synchronous systems. Asynchronous ICs have less stringent environmental constraints and are capable of maintaining reliable operation in extreme environments, while also enjoying potential benefits such as low power consumption, high modularity, and improved performance. However, when the traditional bus architecture of synchronous systems is applied to asynchronous designs, handshaking protocols required for asynchronous circuit operation result in significantly increased power consumption, offsetting the low power benefit of …
Comparison Of Google Image Search And Resnet Image Classification Using Image Similarity Metrics, David Smith
Comparison Of Google Image Search And Resnet Image Classification Using Image Similarity Metrics, David Smith
Computer Science and Computer Engineering Undergraduate Honors Theses
In this paper, we compare the results of ResNet image classification with the results of Google Image search. We created a collection of 1,000 images by performing ten Google Image searches with a variety of search terms. We classified each of these images using ResNet and inspected the results. The ResNet classifier predicted the category that matched the search term of the image 77.5% of the time. In our best case, with the search term “forklift”, the classifier categorized 92 of the 100 images as forklifts. In the worst case, for the category “hammer”, the classifier matched the search term …
Automatic Testing In The United States Air Force, Pearson Wade
Automatic Testing In The United States Air Force, Pearson Wade
Computer Science and Computer Engineering Undergraduate Honors Theses
The need for standardized Automatic Testing Equipment in the United States Department of Defense has brought about new policies and procedures within entities like the United States Air Force. The diversity and lifespan of systems such as jets, missiles, drones, and other electronics have brought on the need for a new system known as the Versatile Depot Automatic Test Station, or VDATS. The VDATS handles the automatic testing of replaceable digital circuits from different systems. I was introduced to this system firsthand during my time as an intern at Tinker AFB, Oklahoma. This new standardized approach to testing a diverse …
Dynamic 3d Network Data Visualization, Brok Stafford
Dynamic 3d Network Data Visualization, Brok Stafford
Computer Science and Computer Engineering Undergraduate Honors Theses
Monitoring network traffic has always been an arduous and tedious task because of the complexity and sheer volume of network data that is being consistently generated. In addition, network growth and new technologies are rapidly increasing these levels of complexity and volume. An effective technique in understanding and managing a large dataset, such as network traffic, is data visualization. There are several tools that attempt to turn network traffic into visual stimuli. Many of these do so in 2D space and those that are 3D lack the ability to display network patterns effectively. Existing 3D network visualization tools lack user …
The 3d Abstract Tile Assembly Model Is Intrinsically Universal, Aaron Koch, Daniel Hader, Matthew J. Patitz
The 3d Abstract Tile Assembly Model Is Intrinsically Universal, Aaron Koch, Daniel Hader, Matthew J. Patitz
Computer Science and Computer Engineering Undergraduate Honors Theses
In this paper, we prove that the three-dimensional abstract Tile Assembly Model (3DaTAM) is intrinsically universal. This means that there is a universal tile set in the 3DaTAM which can be used to simulate any 3DaTAM system. This result adds to a body of work on the intrinsic universality of models of self-assembly, and is specifically motivated by a result in FOCS 2016 showing that any intrinsically universal tile set for the 2DaTAM requires nondeterminism (i.e. undirectedness) even when simulating directed systems. To prove our result we have not only designed, but also fully implemented what we believe to be …
An Embarrassment Of Riches: Data Integration In Vr Pompeii, Adam Schoelz
An Embarrassment Of Riches: Data Integration In Vr Pompeii, Adam Schoelz
Computer Science and Computer Engineering Undergraduate Honors Theses
It is fair to say that Pompeii is the most studied archaeological site in the world. Beyond the extensive remains of the city itself, the timing of its rediscovery and excavation place it in a unique historiographical position. The city has been continuously studied since the 18th century, with historians and archaeologists constantly reevaluating older sources as our knowledge of the ancient world expands. While several studies have approached the city from a data driven perspective, no studies of the city have taken a quantitative holistic approach on the scale of the VR Pompeii project. Hyper-specificity has been the order …
Training Machine Learning Agents In A 3d Game Engine, Diego Calderon
Training Machine Learning Agents In A 3d Game Engine, Diego Calderon
Computer Science and Computer Engineering Undergraduate Honors Theses
Artificial intelligence (AI) and video games benefit from each other. Games provide a challenging domain for testing learning algorithms, and AI provides a framework to designing and implementing intelligent behavior, which reinforces meaningful play. Medium and small studios, and independent game developers, have limited resources to design, implement, and maintain agents with reactive behavior. In this research, we trained agents using machine learning (ML), aiming to find an alternative to expensive traditional algorithms for intelligent behavior used in video games. We use Unity as a game engine to implement the environments and TensorFlow for the neural network training.
A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman
A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman
Graduate Theses and Dissertations
One important aspect of many commercial computer systems is their performance; therefore, system designers seek to improve the performance next-generation systems with respect to previous generations. This could mean improved computational performance, reduced power consumption leading to better battery life in mobile devices, smaller form factors, or improvements in many areas. In terms of increased system speed and computation performance, processor manufacturers have been able to increase the clock frequency of processors up to a point, but now it is more common to seek performance gains through increased parallelism (such as a processor having more processor cores on a single …
Securing Soft Ips Against Hardware Trojan Insertion, Thao Phuong Le
Securing Soft Ips Against Hardware Trojan Insertion, Thao Phuong Le
Graduate Theses and Dissertations
Due to the increasing complexity of hardware designs, third-party hardware Intellectual Property (IP) blocks are often incorporated in order to alleviate the burden on hardware designers. However, the prevalence use of third-party IPs has raised security concerns such as Trojans inserted by attackers. Hardware Trojans in these soft IPs are extremely difficult to detect through functional testing and no single detection methodology has been able to completely address this issue. Based on a Register-Transfer Level (RTL) and gate-level soft IP analysis method named Structural Checking, this dissertation presents a hardware Trojan detection methodology and tool by detailing the implementation of …
Asynchronous Circuit Stacking For Simplified Power Management, Andrew Lloyd Suchanek
Asynchronous Circuit Stacking For Simplified Power Management, Andrew Lloyd Suchanek
Graduate Theses and Dissertations
As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power domains therefore requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area and/or off-chip space, but also aggregate the power loss during the voltage conversions that must occur fast enough to maintain the necessary power supplies. This dissertation work presents an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture that alleviates this problem by reducing the number of voltage converters needed to supply the voltage the …
Modeling Of Cloud-Based Digital Twins For Smart Manufacturing With Mt Connect, Liwen Hu, Ngoc-Tu Nguyen, Wenjin Tao, Ming C. Leu, Xiaoqing Frank Liu, Md Rakib Shahriar, S M Nahian Al Sunny
Modeling Of Cloud-Based Digital Twins For Smart Manufacturing With Mt Connect, Liwen Hu, Ngoc-Tu Nguyen, Wenjin Tao, Ming C. Leu, Xiaoqing Frank Liu, Md Rakib Shahriar, S M Nahian Al Sunny
Computer Science and Computer Engineering Faculty Publications and Presentations
The common modeling of digital twins uses an information model to describe the physical machines. The integration of digital twins into productive cyber-physical cloud manufacturing (CPCM) systems imposes strong demands such as reducing overhead and saving resources. In this paper, we develop and investigate a new method for building cloud-based digital twins (CBDT), which can be adapted to the CPCM platform. Our method helps reduce computing resources in the information processing center for efficient interactions between human users and physical machines. We introduce a knowledge resource center (KRC) built on a cloud server for information intensive applications. An information model …
Energy And Performance Balancing Architecture For Asynchronous Data Processing Platforms, Chien-Wei Lo
Energy And Performance Balancing Architecture For Asynchronous Data Processing Platforms, Chien-Wei Lo
Graduate Theses and Dissertations
The semiconductor industry has been increasingly focused on the energy consumption and heat generation in CMOS-based integrated circuits (ICs) for its dominating impact on the system performance and reliability. Without clock-related timing constraints, asynchronous circuits have demonstrated unique flexibility in performance-energy tradeoffs compared to synchronous designs. This dissertation work presents the architecture capable of balancing energy and performance for asynchronous digital signal processing circuits using the Multi-Threshold NULL Convention Logic (MTNCL). Architecture implementing user-configurable adaptive dynamic voltage scaling (DVS) and data processing core disabling based on the detection and parameterization of system throughput are developed for MTNCL parallel homogeneous and …
Operating System Identification By Ipv6 Communication Using Machine Learning Ensembles, Adrian Ordorica
Operating System Identification By Ipv6 Communication Using Machine Learning Ensembles, Adrian Ordorica
Graduate Theses and Dissertations
Operating system (OS) identification tools, sometimes called fingerprinting tools, are essential for the reconnaissance phase of penetration testing. While OS identification is traditionally performed by passive or active tools that use fingerprint databases, very little work has focused on using machine learning techniques. Moreover, significantly more work has focused on IPv4 than IPv6. We introduce a collaborative neural network ensemble that uses a unique voting system and a random forest ensemble to deliver accurate predictions. This approach uses IPv6 features as well as packet metadata features for OS identification. Our experiment shows that our approach is valid and we achieve …
Introduction To Signal Timing & Traffic Control, Sarah V. Hernandez, Mariah Crew, Karla Diaz-Corro, Taslima Akter
Introduction To Signal Timing & Traffic Control, Sarah V. Hernandez, Mariah Crew, Karla Diaz-Corro, Taslima Akter
Civil Engineering Teaching and Learning
The purpose of these lesson plans is to introduce students to traffic signalization basics. Students will be lead through a series of mini-lectures on traffic control and signalization including a discussion on the limitations and benefits of traffic signalization. The lesson plans compliment a computer simulation “game” in which students act as manual operators for a single up to four by four gridded intersection. Students attempt to control the progression of signals to understand the relationship between signal timing and user delay. Through experimentation with the simulation, students generate a presentation discussing the benefits and drawbacks of signal timing and …
Improving Automatic Content Type Identification From A Data Set, Kathy T. Dai
Improving Automatic Content Type Identification From A Data Set, Kathy T. Dai
Computer Science and Computer Engineering Undergraduate Honors Theses
Data file layout inference refers to building the structure and determining the metadata of a text file. The text files dealt within this research are personal information records that have a consistent structure. Traditionally, if the layout structure of a text file is unknown, the human user must undergo manual labor of identifying the metadata. This is inefficient and prone to error. Content-based oracles are the current state-of-the-art automation technology that attempts to solve the layout inference problem by using databases of known metadata. This paper builds upon the information and documentation of the content-based oracles, and improves the databases …
Music Feature Matching Using Computer Vision Algorithms, Mason Hollis
Music Feature Matching Using Computer Vision Algorithms, Mason Hollis
Computer Science and Computer Engineering Undergraduate Honors Theses
This paper seeks to establish the validity and potential benefits of using existing computer vision techniques on audio samples rather than traditional images in order to consistently and accurately identify a song of origin from a short audio clip of potentially noisy sound. To do this, the audio sample is first converted to a spectrogram image, which is used to generate SURF features. These features are compared against a database of features, which have been previously generated in a similar fashion, in order to find the best match. This algorithm has been implemented in a system that can run as …
Project Pradio, Trigg T. La Tour
Project Pradio, Trigg T. La Tour
Computer Science and Computer Engineering Undergraduate Honors Theses
This paper examines the design and manufacturing of a device that allows two or more users to share a wireless audio stream. Effectively, this allows a group of people to listen to the same audio in a synchronized manner. The product was unable to be completed in the allotted time. Regardless, significant progress was made and valuable insight into the circuit board design process was gained.
A Study Of Activation Functions For Neural Networks, Meenakshi Manavazhahan
A Study Of Activation Functions For Neural Networks, Meenakshi Manavazhahan
Computer Science and Computer Engineering Undergraduate Honors Theses
Artificial neural networks are function-approximating models that can improve themselves with experience. In order to work effectively, they rely on a nonlinearity, or activation function, to transform the values between each layer. One question that remains unanswered is, “Which non-linearity is optimal for learning with a particular dataset?” This thesis seeks to answer this question with the MNIST dataset, a popular dataset of handwritten digits, and vowel dataset, a dataset of vowel sounds. In order to answer this question effectively, it must simultaneously determine near-optimal values for several other meta-parameters, including the network topology, the optimization algorithm, and the number …
A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly Of Custom Accelerators On Fpgas, Zeyad Tariq Aklah
A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly Of Custom Accelerators On Fpgas, Zeyad Tariq Aklah
Graduate Theses and Dissertations
The state of the art in design and development flows for FPGAs are not sufficiently mature to allow programmers to implement their applications through traditional software development flows. The stipulation of synthesis as well as the requirement of background knowledge on the FPGAs' low-level physical hardware structure are major challenges that prevent programmers from using FPGAs. The reconfigurable computing community is seeking solutions to raise the level of design abstraction at which programmers must operate, and move the synthesis process out of the programmers' path through the use of overlays. A recent approach, Just-In-Time Assembly (JITA), was proposed that enables …
Exploiting Hardware Abstraction For Parallel Programming Framework: Platform And Multitasking, Hongyuan Ding
Exploiting Hardware Abstraction For Parallel Programming Framework: Platform And Multitasking, Hongyuan Ding
Graduate Theses and Dissertations
With the help of the parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance of many applications. However, designers are required to have excellent hardware programming skills and unique optimization techniques to explore the potential of FPGA resources fully. Intermediate frameworks above hardware circuits are proposed to improve either performance or productivity by leveraging parallel programming models beyond the multi-core era.
In this work, we propose the PolyPC (Polymorphic Parallel Computing) framework, which targets enhancing productivity without losing performance. It helps designers develop parallelized applications and implement them on FPGAs. …
Power Efficient High Temperature Asynchronous Microcontroller Design, Nathan William Kuhns
Power Efficient High Temperature Asynchronous Microcontroller Design, Nathan William Kuhns
Graduate Theses and Dissertations
There is an increasing demand for dependable and efficient digital circuitry capable of operating in high temperature environments. Extreme temperatures have adverse effects on traditional silicon synchronous systems because of the changes in delay and setup and hold times caused by the variances in each device’s threshold voltage. This dissertation focuses on the design of the major functionality of an asynchronous 8051 microcontroller in Raytheon’s high temperature Silicon Carbide process, rated for operation over 300ºC. The microcontroller is designed in NULL Convention Logic, for which the traditional bus architecture used for data transfer would consume a large amount of power. …
Transportation Engineering: Traffic Control Simulator, Sarah V. Hernandez, Karla Diaz-Corro, Taslima Akter, Magdalena Asborno, Fu Durandal
Transportation Engineering: Traffic Control Simulator, Sarah V. Hernandez, Karla Diaz-Corro, Taslima Akter, Magdalena Asborno, Fu Durandal
Civil Engineering Teaching and Learning
The purpose of these lesson plans is to introduce students to traffic signalization basics. Students will be lead through a series of mini-lectures on traffic control and signalization including a discussion on the limitations and benefits of traffic signalization. The lesson plans compliment a computer simulation “game” in which students act as manual operators for a single up to four by four gridded intersection. Students attempt to control the progression of signals to understand the relationship between signal timing and user delay. Through experimentation with the simulation, students generate a presentation discussing the benefits and drawbacks of signal timing and …
Just In Time Assembly (Jita) - A Run Time Interpretation Approach For Achieving Productivity Of Creating Custom Accelerators In Fpgas, Sen Ma
Graduate Theses and Dissertations
The reconfigurable computing community has yet to be successful in allowing programmers to access FPGAs through traditional software development flows. Existing barriers that prevent programmers from using FPGAs include: 1) knowledge of hardware programming models, 2) the need to work within the vendor specific CAD tools and hardware synthesis. This thesis presents a series of published papers that explore different aspects of a new approach being developed to remove the barriers and enable programmers to compile accelerators on next generation reconfigurable manycore architectures. The approach is entitled Just In Time Assembly (JITA) of hardware accelerators. The approach has been defined …
Asynchronous Data Processing Platforms For Energy Efficiency, Performance, And Scalability, Liang Men
Asynchronous Data Processing Platforms For Energy Efficiency, Performance, And Scalability, Liang Men
Graduate Theses and Dissertations
The global technology revolution is changing the integrated circuit industry from the one driven by performance to the one driven by energy, scalability and more-balanced design goals. Without clock-related issues, asynchronous circuits enable further design tradeoffs and in operation adaptive adjustments for energy efficiency. This dissertation work presents the design methodology of the asynchronous circuit using NULL Convention Logic (NCL) and multi-threshold CMOS techniques for energy efficiency and throughput optimization in digital signal processing circuits. Parallel homogeneous and heterogeneous platforms implementing adaptive dynamic voltage scaling (DVS) based on the observation of system fullness and workload prediction are developed for balanced …
Bluetooth Low Energy Platform With Simblee, Calvin W. Freeman
Bluetooth Low Energy Platform With Simblee, Calvin W. Freeman
Computer Science and Computer Engineering Undergraduate Honors Theses
Bluetooth Low Energy provides a platform for many developers to implement low power communication for a wide range of applications. The Internet of Things (IoT) is an emerging concept that is gaining traction in the world of embedded systems. Bluetooth Low Energy is one of the latest enablers of this movement and the Simblee module improves BLE accessibility. This thesis provides an evaluation of the average power consumption the Simblee uses in different use cases. By leveraging one of the Simblee’s most notable features, the Ultra Low Power mode, very low power consumption can be achieved, potentially increasing battery life …
Inferring Intrinsic Beliefs Of Digital Images Using A Deep Autoencoder, Seok H. Lee
Inferring Intrinsic Beliefs Of Digital Images Using A Deep Autoencoder, Seok H. Lee
Computer Science and Computer Engineering Undergraduate Honors Theses
Training a system of artificial neural networks on digital images is a big challenge. Often times digital images contain a large amount of information and values for artificial neural networks to understand. In this work, the inference model is proposed in order to absolve this problem. The inference model is composed of a parameterized autoencoder that endures the loss of information caused by the rescaling of images and transition model that predicts the effect of an action on the observation. To test the inference model, the images of a moving robotic arm were given as the data set. The inference …