Systems Architecture Commons^™

Kangaroo: Dynamic Fusion Of Branch Instructions In A Pipelined Uniprocessor, Sarah E. Larkin

Dissertations, Master's Theses and Master's Reports

Small pipelined processors are becoming more common as a complement to superscalars in a multi-core chip. However, current uniprocessors offer little in the way of ILP. We present kangaroo, a novel approach to instruction fusion in a pipelined processor. Kangaroo dynamically fuses two adjacent instructions to create a pair that travels through the pipeline as a unit. The instructions re-enter the pipeline as a pair the next time the first instruction is fetched. Unlike in prior art, an instruction, once fused, is not fetched again. Any pair of adjacent instructions can be fused using this technique, including dependent instructions. …

Utilizing Biometrics And Blockchain For Enhanced Security Of Remote Patient Monitoring (Rpm) Data Sharing, Amaturrahman Raihanah Medlock

Dissertations, Master's Theses and Master's Reports

Advancements in Artificial Intelligence (AI) and Internet of Medical Things (IoMT) technologies have significantly revolutionized the conventional healthcare systems. Through the integration of smart devices, medical sensors, and communication technology, IoMT provides real-time patient’s monitoring data for healthcare providers, thus promoting accurate and timely clinical decisions for patient-centric care. The current healthcare sector is evolving to a connected ecosystem with connectivity and intelligence. While it also incurs increasing security and privacy concerns as integrating IoMT generated patient monitoring data into healthcare information systems. Both blockchain and biometrics are measures that have established reputable names in the security realm. When evaluating …

A Virtual Time Driven Simulator For Devs Models, Ronald R. Stempien

Dissertations, Master's Theses and Master's Reports

When simulating a system that includes some software component, simulation authors are faced with the problem of how to appropriately model the software within the simulation. While many formal methods for modeling software exist, in some contexts these may not be appropriate or viable for a given simulation. Instead, simulation authors may model a computer within the simulation, and run the software in question “as is” on the modeled machine. In this work, we introduce a theoretical framework to allow for the use of hardware virtualization technologies as a hardware accelerator for CPU models in Discrete Event System Specification (DEVS) …

Dynamic Memory Management For Key-Value Store, Yuchen Wang

Dissertations, Master's Theses and Master's Reports

To minimize the latency of accessing back-end servers, modern web services often use in-memory key-value (k-v) stores at the front end to cache frequently accessed objects. Due to the limited memory capacity, these stores must be configured with a fixed amount of memory. Consequently, cache replacement is required when the footprint of the accessed objects exceeds the cache size.

This thesis presents a comprehensive exploration of advanced dynamic memory management techniques for k-v stores. The first study conducts a detailed analysis of K-LRU, a random sampling-based replacement policy, proposing a dynamic K configuration scheme to exploit the potential miss ratio …

Model Guided Memory Optimization For Key-Value Caches, Daniel Byrne

Dissertations, Master's Theses and Master's Reports

Modern web services deploy key-value caches to store popular requests to backend systems. As such, how the cache stores data impacts both the cache miss ratio and throughput. Therefore, in this thesis, we introduce and apply cache modeling techniques to optimize the memory organization of a key-value cache to improve overall cache performance.

Specifically, we begin with a single-level key-value cache and use miss ratio curves to adjust the memory assigned to the residing applications dynamically. This leads to an improvement in miss ratio up to 25% over state-of-the-art techniques and an 8.8% improvement in cache throughput. We then consider …

Statically Controlled Synchronized Lane Architectures, Scott K. Pomerville

Dissertations, Master's Theses and Master's Reports

Modern superscalar processors dominate the field of computing. While dynamic execution allows for versatility in code, these processors are complex. Statically scheduled code has historically enabled simpler processor designs, but static scheduling cannot account for variables that are unknown at compile time. Furthermore, static scheduling has many inefficiencies, such as the need to insert a large number of nops for code in traditional Very Long Instruction Word (VLIW) processors. In this dissertation, we explore a novel architectural approach for statically scheduled code by breaking the code into several synchronous instruction streams. By representing code in a fundamentally new way, we …

Exploring High Performance And Energy Efficient Graph Processing On Gpu, Robert P. Watling

Dissertations, Master's Theses and Master's Reports

Parallel graph processing is central to analytical computer science applications, and GPUs have proven to be an ideal platform for parallel graph processing. Existing GPU graph processing frameworks present performance improvements but often neglect two issues: the unpredictability of a given input graph and the energy consumption of the graph processing. Our prototype software, EEGraph (Energy Efficiency of Graph processing), is a flexible system consisting of several graph processing algorithms with configurable parameters for vertex update synchronization, vertex activation, and memory management along with a lightweight software-based GPU energy measurement scheme. We observe relationships between different configurations of our software, …

Poor Man’S Trace Cache: A Variable Delay Slot Architecture, Tino C. Moore

Dissertations, Master's Theses and Master's Reports

We introduce a novel fetch architecture called Poor Man’s Trace Cache (PMTC). PMTC constructs taken-path instruction traces via instruction replication in static code and inserts them after unconditional direct and select conditional direct control transfer instructions. These traces extend to the end of the cache line. Since available space for trace insertion may vary by the position of the control transfer instruction within the line, we refer to these fetch slots as variable delay slots. This approach ensures traces are fetched along with the control transfer instruction that initiated the trace. Branch, jump and return instruction semantics as well as …

Virtual Machine Introspection Tool Design Analysis, Justin Martin

Dissertations, Master's Theses and Master's Reports

Virtual machines are an integral part of today’s computing world. Their use is widespread and applicable in many different computing fields. With virtual machines, the ability to introspect and monitor is often overlooked or left unimplemented. Introspection is used to gather information about the state of virtual machines as they operate. Without introspection, verbose log data and state information is unavailable after unexpected errors or crashes occur. With introspection, this data can be analyzed further to determine the true cause of the unexpected crash or error. Therefore, introspection plays a critical role in portraying accurate historical information regarding the operating …

Efficient Modeling Of Random Sampling-Based Lru Cache, Junyao Yang

Dissertations, Master's Theses and Master's Reports

The Miss Ratio Curve (MRC) is an important metric and effective tool for caching system performance prediction and optimization. Since the Least Recently Used (LRU) replacement policy is the de facto policy for many existing caching systems, most previous studies on efficient MRC construction are predominantly focused on the LRU replacement policy. Recently, the random sampling-based replacement mechanism, as opposed to replacement relying on the rigid LRU data structure, gains more popularity due to its lightweight and flexibility. To approximate LRU, at replacement times, the system randomly selects K objects and replaces the least recently used object among the sample. …

Demand-Driven Execution Using Future Gated Single Assignment Form, Omkar Javeri

Dissertations, Master's Theses and Master's Reports

This dissertation discusses a novel, previously unexplored execution model called Demand-Driven Execution (DDE), which executes programs starting from the outputs of the program, progressing towards the inputs of the program. This approach is significantly different from prior demand-driven reduction machines as it can execute a program written in an imperative language using the demand-driven paradigm while extracting both instruction and data level parallelism. The execution model relies on an executable Single Assignment Form which serves both as the internal representation of the compiler as well as the Instruction Set Architecture (ISA) of the machine. This work develops the instruction set …

Contextual Bandit Modeling For Dynamic Runtime Control In Computer Systems, Jason Hiebel

Dissertations, Master's Theses and Master's Reports

Modern operating systems and microarchitectures provide a myriad of mechanisms for monitoring and affecting system operation and resource utilization at runtime. Dynamic runtime control of these mechanisms can tailor system operation to the characteristics and behavior of the current workload, resulting in improved performance. However, developing effective models for system control can be challenging. Existing methods often require extensive manual effort, computation time, and domain knowledge to identify relevant low-level performance metrics, relate low-level performance metrics and high-level control decisions to workload performance, and to evaluate the resulting control models.

This dissertation develops a general framework, based on the contextual …

Modeling Data Center Co-Tenancy Performance Interference, Wei Kuang

Dissertations, Master's Theses and Master's Reports

A multi-core machine allows executing several applications simultaneously. Those jobs are scheduled on different cores and compete for shared resources such as the last level cache and memory bandwidth. Such competitions might cause performance degradation. Data centers often utilize virtualization to provide a certain level of performance isolation. However, some of the shared resources cannot be divided, even in a virtualized system, to ensure complete isolation. If the performance degradation of co-tenancy is not known to the cloud administrator, a data center often has to dedicate a whole machine for a latency-sensitive application to guarantee its quality of service. Co-run …