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Articles 31 - 60 of 67
Full-Text Articles in VLSI and Circuits, Embedded and Hardware Systems
Idpal – A Partially-Adiabatic Energy-Efficient Logic Family: Theory And Applications To Secure Computing, Mihail T. Cutitaru
Idpal – A Partially-Adiabatic Energy-Efficient Logic Family: Theory And Applications To Secure Computing, Mihail T. Cutitaru
Electrical & Computer Engineering Theses & Dissertations
Low-power circuits and issues associated with them have gained a significant amount of attention in recent years due to the boom in portable electronic devices. Historically, low-power operation relied heavily on technology scaling and reduced operating voltage, however this trend has been slowing down recently due to the increased power density on chips. This dissertation introduces a new very-low power partially-adiabatic logic family called Input-Decoupled Partially-Adiabatic Logic (IDPAL) with applications in low-power circuits. Experimental results show that IDPAL reduces energy usage by 79% compared to equivalent CMOS implementations and by 25% when compared to the best adiabatic implementation. Experiments ranging …
Digital Display With Integrated Computing Circuit, Ronald S. Cok, John W. Harmer, Michael E. Miller
Digital Display With Integrated Computing Circuit, Ronald S. Cok, John W. Harmer, Michael E. Miller
AFIT Patents
A digital display device includes a display substrate; an array of pixels formed on the display substrate; an array of driving circuits located on the display substrate, each driving circuit electrically connected to one or more pixels for controlling a pixel current provided to each pixel; an array of computing circuits located on the display substrate, each computing circuit including circuits for signal or image processing and for communicating with neighboring computing circuits; a plurality of electrical conductors formed on the display substrate and connected to each of the driving circuits and digital computing circuits, wherein each computing circuit is …
Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker
Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker
College of Engineering: Graduate Celebration Programs
As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. Although Static-Timing Analysis (STA) remains an excellent tool, current trends in process scaling have imposed significant difficulties to STA. As one of the promising solutions, Statistical static timing analysis (SSTA) has become the frontier research topic in recent years in combating such variation effects. This poster will be focusing on two aspects of SSTA and its applications in VLSI designs: (1) Statistical timing modeling and analysis; and (2) Architectural implementations of the atomic operations (max and add) using …
Ultra-Low Voltage Digital Circuits And Extreme Temperature Electronics Design, Aaron J. Arthurs
Ultra-Low Voltage Digital Circuits And Extreme Temperature Electronics Design, Aaron J. Arthurs
Graduate Theses and Dissertations
Certain applications require digital electronics to operate under extreme conditions e.g., large swings in ambient temperature, very low supply voltage, high radiation. Such applications include sensor networks, wearable electronics, unmanned aerial vehicles, spacecraft, and energyharvesting systems. This dissertation splits into two projects that study digital electronics supplied by ultra-low voltages and build an electronic system for extreme temperatures. The first project introduces techniques that improve circuit reliability at deep subthreshold voltages as well as determine the minimum required supply voltage. These techniques address digital electronic design at several levels: the physical process, gate design, and system architecture. This dissertation analyzes …
Asynchronous Mips Processors: Educational Simulations, Robert L. Webb
Asynchronous Mips Processors: Educational Simulations, Robert L. Webb
Master's Theses
The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …
Hand-Held Flyback Driven Coaxial Dielectric Barrier Discharge: Development And Characterization, Victor J. Law, Vladimir Milosavljevic, Neil O’Connor, James F. Lalor, Steven Daniels
Hand-Held Flyback Driven Coaxial Dielectric Barrier Discharge: Development And Characterization, Victor J. Law, Vladimir Milosavljevic, Neil O’Connor, James F. Lalor, Steven Daniels
Articles
The development of a handheld single and triple chamber atmospheric pressure coaxial dielectric barrier discharge driven by Flyback circuitry for helium and argon discharges is described. The Flyback uses external metal-oxide-semiconductor field-effect transistor power switching technology and the transformer operates in the continuous current mode to convert a continuous dc power of 10–33 W to generate a 1.2–1.6 kV 3.5 μs pulse. An argon discharge breakdown voltage of ∼768 V is measured. With a 50 kHz, pulse repetition rate and an argon flow rate of 0.5–10 argon slm (slm denotes standard liters per minute), the electrical power density deposited in …
Unidirectional Cordic For Efficient Computation Of Trigonometric And Hyperbolic Functions, Satish Ravichandran
Unidirectional Cordic For Efficient Computation Of Trigonometric And Hyperbolic Functions, Satish Ravichandran
Electrical & Computer Engineering Theses & Dissertations
CORDIC (Coordinate Rotation Digital Computer) is an iterative algorithm to compute values of trigonometric, logarithmic and transcendental functions by performing vector rotations, which can be implemented with only shift and add operations in a digital system. CORDIC algorithms are extensively used in the areas of digital signal processing, digital image processing and artificial neural networks. A new technique, named unidirectional CORDIC, for efficient computation of trigonometric and hyperbolic functions is presented in this thesis. In the conventional CORDIC algorithm, the vector rotations are performed in both clockwise and counterclockwise directions, but in the unidirectional CORDIC the vectors are rotated only …
Parallel Implementation Of A Face Recognition [Sic] System Based On Modular Pca Approach, Rajkiran Gottumukkal
Parallel Implementation Of A Face Recognition [Sic] System Based On Modular Pca Approach, Rajkiran Gottumukkal
Electrical & Computer Engineering Theses & Dissertations
This thesis describes research in automated methods for the recognition of human faces. The research is driven by the need to design a method, which would ensure high accuracy under the conditions of facial expression, illumination and pose variations. The resulting method is able to cope with uncontrolled nature of facial expression, illumination and head rotations. The main novelty of this work is the idea that some of the local facial features do not vary even when the facial expression, illumination and pose vary. This idea is applied to the existing principle component analysis lPCA) method to arrive at a …
On The Area Of Hypercube Layouts, Ronald I. Greenberg, Lee Guan
On The Area Of Hypercube Layouts, Ronald I. Greenberg, Lee Guan
Computer Science: Faculty Publications and Other Works
This paper precisely analyzes the wire density and required area in standard styles for the hypercube. It shows that the most natural, regular layout of a hypercube of N^2 nodes in the plane, in a NxN grid arrangement, uses floor(2N/3)+1 horizontal wiring tracks for each row of nodes. (In the process, we see that the number of tracks per row can be reduced by 1 with a less regular design, as can also be seen from an independent argument of Bezrukov et al.) This paper also gives a simple formula for the wire density at any cut position and a …
A Vhdl Implementation Of Bist Technique In Uart Design, Mohd. Yamani Idna Idris
A Vhdl Implementation Of Bist Technique In Uart Design, Mohd. Yamani Idna Idris
Student Works (2000-2009)
No abstract provided.
Vhdl Implementation For Jawi Character Recognition, Mustafa Norita Adila
Vhdl Implementation For Jawi Character Recognition, Mustafa Norita Adila
Student Works (2000-2009)
Kewujudan tulisan jawi sejak dahulu lagi telah menghasilkan pelbagai karya penting dalam perkembangan islam. Sebagai satu bahasa pengantara, tulisan jawi dianggap penting dalam bidang penulisan. Tidak terhad hanya kepada buku-buku, dokumen-dokumen dan manuskrip-manuskrip yang ditulis dalam tulisan jawi, malah penggunaanya amat meluas dan meliputi keseluruhan bidang. Menyedari kepentingannya, timbul minat saya untuk mengkaji dengan lebih mendalam bagaimana komputer boleh mengenali dan memahami tulisan ini tanpa menggunakan tenaga manusia berdasarkan kepada beberapa kajian yang sedia ada yang telah dijalankan oleb mereka yang pakar dalam teknologi komputer digital. Secara keseluruhan, kajian ini akan membantu memudahkan lagi pengecaman tulisan tangan jawi yang dilakukan …
Keyboard - Smart Card Reader Controller Using Vhdl, Lani Mohd Zuwairi
Keyboard - Smart Card Reader Controller Using Vhdl, Lani Mohd Zuwairi
Student Works (2000-2009)
As the time fly by the technology of computers has improves and much security is needed in every transaction of data that being done. In this project, designing a microcontroller for keyboard and smart card reader terminal integration is being done. At first stage, the architecture of the controller will analyze and studied. This will need some practice of knowledge in computer organization and architecture, as well as microprocessors architecture designs. Then the architecture is design using hardware prototyping. This is by using the VHSIC Hardware Description Language (VHDL). The codes done using the language then being simulate to get …
Litar Aritmetik Reja, Abd. Mutalib Leorna Shazerine
Litar Aritmetik Reja, Abd. Mutalib Leorna Shazerine
Student Works (2000-2009)
Projek Ilmiah Tahap Akhir II, iaitu WXES 3182 adalah suatu latihan akademik di dalam penyelidikan, rekabentuk, pembangunan dan komunikasi yang melibatkan prinsip-prinsip sains komputer. Projek WXES 3182 ini merupakan kursus pelengkap bagi pelajar-pelajar tahun akhir untuk mendapatkan penganugerahan Sarjana Muda Sains Komputer. Projek WXES 3182 ini adalah kesinabungan daripada projek WXES 3181 Kajian penyehdikan yang telah dijalankan adalah berkaitan dengan konsep sistem nombor reja dan litar aritmetik reja. Laporan latihan ilmiah tahap akhir II ini, merangkumi pembangunan projek WXES 3181 dan WXES 3182. laporan ini terdiri daripada lapan bahagian dan diantaranya ialah pengenalan kepada projek, kajian literasi, metodologi yang digunakan …
Vhdl Description For Ip Engine, Bathich Zeliall
Vhdl Description For Ip Engine, Bathich Zeliall
Student Works (2000-2009)
Developing hardware support for network layer protocol processing is a very complex and demanding task. However. for optimal performance hardware acceleration can be required. To cope with the situation. this project present a high-level design approach. which targets the development of configurable and reusable components. Therefore it obtains the integration of advanced tools for the development of the IP Engine into the design environment. This process is illustrated based on a TCP/IP header analysis and validation component for which initial performance results are presented. The development of this Engine is embedded in an approach to develop flexible and configurable protocol …
Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih
Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih
Computer Science: Faculty Publications and Other Works
We give algorithms to minimize density for VLSI channel routing problems with terminals that are movable subject to certain constraints. The main cases considered are channels with linear order constraints, channels with linear order constraints and separation constraints, channels with movable modules containing fixed terminals, and channels with movable modules and terminals. In each case, we improve previous results for running time and space by a factor of L/\lgn and L, respectively, where L is the channel length, and n is the number of terminals.
Parallel Algorithms For Single-Layer Channel Routing, Ronald I. Greenberg, Shih-Chuan Hung, Jau-Der Shih
Parallel Algorithms For Single-Layer Channel Routing, Ronald I. Greenberg, Shih-Chuan Hung, Jau-Der Shih
Computer Science: Faculty Publications and Other Works
We provide efficient parallel algorithms for the minimum separation, offset range, and optimal offset problems for single-layer channel routing. We consider all the variations of these problems that are known to have linear- time sequential solutions rather than limiting attention to the "river-routing" context, where single-sided connections are disallowed. For the minimum separation problem, we obtain O(lgN) time on a CREW PRAM or O(lgN / lglgN) time on a (common) CRCW PRAM, both with optimal work (processor- time product) of O(N), where N is the number of terminals. For the offset range problem, we obtain the same time and processor …
An Empirical Comparison Of Area-Universal And Other Parallel Computing Networks, Ronald I. Greenberg, Lee Guan
An Empirical Comparison Of Area-Universal And Other Parallel Computing Networks, Ronald I. Greenberg, Lee Guan
Computer Science: Faculty Publications and Other Works
This paper provides empirical comparison of the communication capabilities of two area-universal networks, the fat-tree and the fat-pyramid, to the popular mesh and hypercube networks for parallel computation. While area-universal networks have been proven capable of simulating, with modest slowdown, any computation of any other network of comparable area, prior work has generally left open the question of how area-universal networks compare to other networks in practice. Comparisons are performed using techniques of throughput and latency analysis that have previously been applied to k-ary n-cube networks and using various existing models to equate the hardware cost of the networks being …
Single-Layer Channel Routing And Placement With Single-Sided Nets, Ronald I. Greenberg, Jau-Der Shih
Single-Layer Channel Routing And Placement With Single-Sided Nets, Ronald I. Greenberg, Jau-Der Shih
Computer Science: Faculty Publications and Other Works
This paper considers the optimal offset, feasible offset, and optimal placement problems for a more general form of single-layer VLSI channel routing than has usually been considered in the past. Most prior works require that every net has exactly one terminal on each side of the channel. As long as only one side of the channel contains multiple terminals of the same net, we provide linear-time solutions to all three problems. Such results are implausible if the placement of terminals is entirely unrestricted; in fact, the size of the output for the feasible offset problem may be Ω(n^2). The linear-time …
The Fat-Pyramid And Universal Parallel Computation Independent Of Wire Delay, Ronald I. Greenberg
The Fat-Pyramid And Universal Parallel Computation Independent Of Wire Delay, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
This paper shows that a fat-pyramid of area Θ(A) requires only O(log A) slowdown to simulate any competing network of area A under very general conditions. The result holds regardless of the processor size (amount of attached memory) and number of processors in the competing networks as long as the limitation on total area is met. Furthermore, the result is valid regardless of the relationship between wire length and wire delay. We especially focus on elimination of the common simplifying assumption that unit time suffices to traverse a wire regardless of its length, since the assumption becomes more and more …
Parallel Algorithms For Single-Layer Channel Routing, Ronald I. Greenberg, Shih-Chuan Hung, Jau-Der Shih
Parallel Algorithms For Single-Layer Channel Routing, Ronald I. Greenberg, Shih-Chuan Hung, Jau-Der Shih
Computer Science: Faculty Publications and Other Works
We provide efficient parallel algorithms for the minimum separation, offset range, and optimal offset problems for single-layer channel routing. We consider all the variations of these problems that have linear-time sequential solutions rather than limiting attention to the ``river-routing'' context, where single-sided connections are disallowed. For the minimum separation problem, we obtain O(lgN) time on a CREW PRAM or O(lgN/lglgN) time on a CRCW PRAM, both with optimal work (processor-time product) of O(N), where N is the number of terminals. For the offset range problem, we obtain the same time and processor bounds as long as only one side of …
Feasible Offset And Optimal Offset For Single-Layer Channel Routing, Ronald I. Greenberg, Jau-Der Shih
Feasible Offset And Optimal Offset For Single-Layer Channel Routing, Ronald I. Greenberg, Jau-Der Shih
Computer Science: Faculty Publications and Other Works
The paper provides an efficient method to find all feasible offsets for a given separation in a VLSI channel routing problem in one layer. The prior literature considers this task only for problems with no single-sided nets. When single-sided nets are included, the worst-case solution time increases from Theta(n) to Omega(n^2), where n is the number of nets. But, if the number of columns c is O(n), one can solve the problem in time O(n^{1.5}lg n ), which improves upon a `naive' O(cn) approach. As a corollary of this result, the same time bound suffices to find the optimal offset …
A Systolic Simulation And Transformation System, Ronald I. Greenberg, H.-C. Oh
A Systolic Simulation And Transformation System, Ronald I. Greenberg, H.-C. Oh
Computer Science: Faculty Publications and Other Works
This paper presents a CAD tool, SystSim, to ease the design of systolic systems. Given a high-level, functional description of processors, and a high-level description of their interconnection, SystSim will perform simulations and provide graphical output. SystSim will also perform transformations such as retiming, which eases use of the methodology of Leiserson and Saxe of designing a system with broadcasting and then obtaining a systolic system through retiming.
Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih
Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih
Computer Science: Faculty Publications and Other Works
We give algorithms to minimize density for channels with terminals that are movable subject to certain constraints. The main cases considered are channels with linear order constraints, channels with linear order constraints and separation constraints, channels with movable modules containing fixed terminals, and channels with movable modules and terminals. In each case, previous results for running time and space are improved by a factor of L/lg n and L , respectively, where L is the channel length and n is the number of terminals.
A Generic Template Extractor (Gentex) In C For Vlsi Design Verification, Kenneth J. Mcclellan Jr.
A Generic Template Extractor (Gentex) In C For Vlsi Design Verification, Kenneth J. Mcclellan Jr.
Theses and Dissertations
The problem of VLSI design verification through circuit extraction was analyzed. The problems of creating a simple template format, the permutability of pins, maintaining connectivity, and performance were focused on. A generic template extractor (GENTEX) was developed in the C programming language for use as a testbed to find solutions to these problems. Six different extraction algorithms were tested with GENTEX and compared based on performance. EDIF translation programs were used to interface with GENTEX on both the input and output sides. One translation program converted an EDIF representation of a schematic into the template format used by GENTEX. The …
On The Difficulty Of Manhattan Channel Routing, Ronald I. Greenberg, Joseph Jaja, Sridhar Krishnamurthy
On The Difficulty Of Manhattan Channel Routing, Ronald I. Greenberg, Joseph Jaja, Sridhar Krishnamurthy
Computer Science: Faculty Publications and Other Works
We show that channel routing in the Manhattan model remains difficult even when all nets are single-sided. Given a set of n single-sided nets, we consider the problem of determining the minimum number of tracks required to obtain a dogleg-free routing. In addition to showing that the decision version of the problem isNP-complete, we show that there are problems requiring at least d+Omega(sqrt(n)) tracks, where d is the density. This existential lower bound does not follow from any of the known lower bounds in the literature.
Version And Transaction Management In Osmagic: An Object-Oriented Database Implementation Of The Magic Vlsi Layout Design Tool, Gary M. Lightner
Version And Transaction Management In Osmagic: An Object-Oriented Database Implementation Of The Magic Vlsi Layout Design Tool, Gary M. Lightner
Theses and Dissertations
The goal of this thesis was to study the feasibility of using an object-oriented database management system to provide the functionality and performance needed to support a complex computer-aided design tool. We do this by modifying OSMagic, a prototype system of the Magic very large scale integrated (VLSI) circuit design tool implemented on the ObjectStore object- oriented database management system. OSMagic was changed to support three different interfaces to ObjectStore and to work in a networking environment. We then designed and examined the use of version and transaction management models as a means of addressing the weaknesses of the prototype …
Minimum Separation For Single-Layer Channel Routing, Ronald I. Greenberg, F. Miller Maley
Minimum Separation For Single-Layer Channel Routing, Ronald I. Greenberg, F. Miller Maley
Computer Science: Faculty Publications and Other Works
We present a linear-time algorithm for determining the minimum height of a single-layer routing channel. The algorithm handles single-sided connections and multiterminal nets. It yields a simple routability test for single-layer switchboxes, correcting an error in the literature.
Hardware-Verification Through Logic Extraction, Michael A. Dukes
Hardware-Verification Through Logic Extraction, Michael A. Dukes
Theses and Dissertations
A Prolog-based system is described which employs logic-extraction to perform hardware-verification. The extraction rules are built automatically from hierarchical structural VHDL models, enabling the equivalence of a structural VHDL description and a layout specification to be verified. Pin-to-pin critical- path analysis is performed within the logic-extraction process; many noncritical paths are pruned early, making pin-to-pin critical path analysis of large circuits feasible. It is demonstrated that a design methodology based on logic extraction, VHDL, and a layout tool can provide a fabricated functionally- correct IC design without circuit-level or switch-level simulation. This methodology is shown to be practical for VLSI …
Finding A Maximum-Density Planar Subset Of A Set Of Nets In A Channel, Ronald I. Greenberg, Jau-Der Shih
Finding A Maximum-Density Planar Subset Of A Set Of Nets In A Channel, Ronald I. Greenberg, Jau-Der Shih
Computer Science: Faculty Publications and Other Works
We present efficient algorithms to find a maximum-density planar subset of n 2-pin nets in a channel. The simplest approach is to make repeated usage of Supowit's dynamic programming algorithm for finding a maximum-size planar subset, which leads to O(n^3) time to find a maximum-density planar subset. But we also provide an algorithm whose running time is dependent on other problem parameters and is often more efficient. A simple bound on the running time of this algorithm is O(nlgn+n(t+1)w), where t is the number of two-sided nets, and w is the number of nets in the output. Though the worst-case …
An Object-Oriented Database Implementation Of The Magic Vlsi Layout Design System, Timothy M. Jacobs
An Object-Oriented Database Implementation Of The Magic Vlsi Layout Design System, Timothy M. Jacobs
Theses and Dissertations
This thesis attempts to prove that the commercially available Object Store data management system provide the performance and functionality necessary to support a complex engineering design system. This is accomplished by modifying the Magic VLSI circuit layout design system to eliminate its current Unix file data management system and replace it with Object Store. The approach to this research effort includes a design recovery of the Magic system and identification of its ket data management functions. These functions are then modified to take advantage of the database management facilities of Object Store. Additional code is added to instrument performance measurement …