VLSI and Circuits, Embedded and Hardware Systems Commons^™

Autonomous Uav Battery Swapping, Reed Jacobsen, Nikolai Ruhe, Nathan Dornback

Williams Honors College, Honors Research Projects

One of the main hindrances of unmanned aerial vehicle (UAV) technology are power constraints. One way to alleviate some power constraints would be for two UAVs to exchange batteries while both are in flight. Autonomous mid-air battery swapping will expand the scope of UAV technology by allowing for indefinite flight times and longer missions. A single board computer will control each UAV’s flight software to respond to inputs to align with each other mid-flight. When the two UAVs have joined, mechanical components will exchange a depleted battery on the worker UAV for a freshly charged battery that belongs to the …

Design And Simulation Of An 8-Bit Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter, Sumit K. Verma

Electrical Engineering Theses

The thesis initially investigates the history of the monolithic ADCs. The next chapter explores the different types of ADCs available in the market today. Next, the operation of a 4-bit SAR ADC has been studied. Based on this analysis, an 8-bit charge-redistribution SAR ADC has been designed and simulated with Multisim (National Instruments, Austin, TX). The design is divided into different blocks which are individually implemented and tested. Level-1 SPICE MOSFET models representative of 5μm devices were used wherever individual MOSFETs were used in the design. Finally, the power dissipation during the conversion period was also estimated. The supply voltage …

Autonomous Speed Control For Kia Optima, Andrew J. Combs, Kyle Fugatt, Kevin Mcfall

The Kennesaw Journal of Undergraduate Research

The standard method for speed control is the cruise control system built into most modern vehicles. These systems employ a PID controller which actuates the accelerator thus, in turn, maintains the desired vehicle speed. The main drawback of such a system is that typically the cruise control will only engage above 25 mph. The goal of this paper is to describe a system which we used to control vehicle speed from a stop to any desired speed using an Arduino microcontroller and a CAN BUS shield, from where autonomous features can be built upon. With this system, we were able …

Remote Cable Gantry, Allen L. Bailey

Electrical Engineering

The Remote Cable Gantry is a robotic system that was initially intended to aid in the art of aerial videography. It was designed to enable novice and expert users alike to capture both video footage and audio from perspectives unachievable by current methods. This system uses a series of cables to control the position of a camera gimbal in a defined 3D space and, as a self-contained unit, is portable and easy to use. The Remote Cable Gantry offers a quiet, intuitive, and safe alternative to existing technology, which has been limiting the market and potential of aerial photography and …

Project Pradio, Trigg T. La Tour

Computer Science and Computer Engineering Undergraduate Honors Theses

This paper examines the design and manufacturing of a device that allows two or more users to share a wireless audio stream. Effectively, this allows a group of people to listen to the same audio in a synchronized manner. The product was unable to be completed in the allotted time. Regardless, significant progress was made and valuable insight into the circuit board design process was gained.

Hexarray: A Novel Self-Reconfigurable Hardware System, Fady Hussein

Boise State University Theses and Dissertations

Evolvable hardware (EHW) is a powerful autonomous system for adapting and finding solutions within a changing environment. EHW consists of two main components: a reconfigurable hardware core and an evolutionary algorithm. The majority of prior research focuses on improving either the reconfigurable hardware or the evolutionary algorithm in place, but not both. Thus, current implementations suffer from being application oriented and having slow reconfiguration times, low efficiencies, and less routing flexibility. In this work, a novel evolvable hardware platform is proposed that combines a novel reconfigurable hardware core and a novel evolutionary algorithm.

The proposed reconfigurable hardware core is a …

Design Automation For Carbon Nanotube Circuits Considering Performance And Security Optimization, Lin Liu

Dissertations, Master's Theses and Master's Reports

As prevailing copper interconnect technology advances to its fundamental physical limit, interconnect delay due to ever-increasing wire resistivity has greatly limited the circuit miniaturization. Carbon nanotube (CNT) interconnects have emerged as promising replacement materials for copper interconnects due to their superior conductivity. Buffer insertion for CNT interconnects is capable of improving circuit timing of signal nets with limited buffer deployment. However, due to the imperfection of fabricating long straight CNT, there exist significant unidimensional-spatially correlated variations on the critical CNT geometric parameters such as the diameter and density, which will affect the circuit performance.

This dissertation develops a novel timing …

A Hierarchical Architectural Framework For Securing Unmanned Aerial Systems, Matthew Leccadito

Theses and Dissertations

Unmanned Aerial Systems (UAS) are becoming more widely used in the new era of evolving technology; increasing performance while decreasing size, weight, and cost. A UAS equipped with a Flight Control System (FCS) that can be used to fly semi- or fully-autonomous is a prime example of a Cyber Physical and Safety Critical system. Current Cyber-Physical defenses against malicious attacks are structured around security standards for best practices involving the development of protocols and the digital software implementation. Thus far, few attempts have been made to embed security into the architecture of the system considering security as a holistic problem. …

Analog Spiking Neuromorphic Circuits And Systems For Brain- And Nanotechnology-Inspired Cognitive Computing, Xinyu Wu

Boise State University Theses and Dissertations

Human society is now facing grand challenges to satisfy the growing demand for computing power, at the same time, sustain energy consumption. By the end of CMOS technology scaling, innovations are required to tackle the challenges in a radically different way. Inspired by the emerging understanding of the computing occurring in a brain and nanotechnology-enabled biological plausible synaptic plasticity, neuromorphic computing architectures are being investigated. Such a neuromorphic chip that combines CMOS analog spiking neurons and nanoscale resistive random-access memory (RRAM) using as electronics synapses can provide massive neural network parallelism, high density and online learning capability, and hence, paves …

Asynchronous Data Processing Platforms For Energy Efficiency, Performance, And Scalability, Liang Men

Graduate Theses and Dissertations

The global technology revolution is changing the integrated circuit industry from the one driven by performance to the one driven by energy, scalability and more-balanced design goals. Without clock-related issues, asynchronous circuits enable further design tradeoffs and in operation adaptive adjustments for energy efficiency. This dissertation work presents the design methodology of the asynchronous circuit using NULL Convention Logic (NCL) and multi-threshold CMOS techniques for energy efficiency and throughput optimization in digital signal processing circuits. Parallel homogeneous and heterogeneous platforms implementing adaptive dynamic voltage scaling (DVS) based on the observation of system fullness and workload prediction are developed for balanced …

Cal Poly Supermileage Electronic Fuel Injection, Alexander Pink

Electrical Engineering

Cal Poly Supermileage is a student-run engineering club that builds prototype gasoline vehicles optimized maximum fuel-efficiency. To power their vehicles, the Supermileage team makes use of single-cylinder, 4-stroke, electronically fuel-injected (EFI) gasoline engines. This report details the development, iterative design & test cycles, and integration of an EFI system for the Supermileage club. This project develops an EFI system that interfaces to the most common types of sensors found in the low-power Supermileage-range of engines, including throttle-position sensors, manifold absolute pressure sensors, gear-tooth hall-effect sensors, variable-reluctance position sensors, engine coolant temperature sensors, intake air temperature sensors, and exhaust oxygen sensors. …

El Capitán: Cal Poly Rose Float Digital Drive System, Gregory Raffi Baghdikian

Computer Engineering

In today’s world of smartphones, self-driving cars, and internet-connected coffee makers, it seems as if computers are contained in everything around us. These “embedded systems” have become critical components of our lives, improving everything about the things they control, from cost, to speed, to simplicity. One area that embedded systems has hardly gained a foothold is in the world of floatbuilding. Most of the floats in the Tournament of Roses Parade, including the one built jointly by Cal Poly San Luis Obispo and Cal Poly Pomona, are technologically very simple, using mostly analog components and rudimentary discrete digital logic to …

A Stroke Therapy Brace Design, Evan Kirkbride

Electrical Engineering

Victims of stroke often have difficulty with rehabilitation. With limited movement on their affected arm, patients often do not want to move much for physical therapy. In this project, we design a robotic brace that helps stroke patients move their arm more effectively in a reaching or pulling motion. By giving patients more movement in their affected arm than they would have otherwise, patients gain more from rehabilitation. The brace also adapts to the patient’s needs, providing more inclination or resistance as needed for their physical therapy. This kind of therapy engages patients rather than relying on their likely dwindled …

Prevention Of Drone Jamming Using Hardware Sandboxing, Joshua Mead

Graduate Theses and Dissertations

In this thesis, we concern ourselves with the security of drone systems under jamming-based attacks. We explore a relatively new concept we previously devised, known as hardware sandboxing, to provide runtime monitoring of boundary signals and isolation through resource virtualization for non-trusted system-on-chip (SoC) components. The focus of this thesis is the synthesis of this design and structure with the anti-jamming, security needs of drone systems. We utilize Field Programmable Gate Array (FPGA) based development and target embedded Linux for our hardware sandbox and drone hardware/software system.

We design and implement our working concept on the Digilent Zybo FPGA, which …

An Investigation Into Partitioning Algorithms For Automatic Heterogeneous Compilers, Antonio M. Leija

Master's Theses

Automatic Heterogeneous Compilers allows blended hardware-software solutions to be explored without the cost of a full-fledged design team, but limited research exists on current partitioning algorithms responsible for separating hardware and software. The purpose of this thesis is to implement various partitioning algorithms onto the same automatic heterogeneous compiler platform to create an apples to apples comparison for AHC partitioning algorithms. Both estimated outcomes and actual outcomes for the solutions generated are studied and scored. The platform used to implement the algorithms is Cal Poly’s own Twill compiler, created by Doug Gallatin last year. Twill’s original partitioning algorithm is chosen …

Design And Verification Environment For High-Performance Video-Based Embedded Systems, Michael Mefenza Nentedem

Graduate Theses and Dissertations

In this dissertation, a method and a tool to enable design and verification of computation demanding embedded vision-based systems is presented. Starting with an executable specification in OpenCV, we provide subsequent refinements and verification down to a system-on-chip prototype into an FPGA-Based smart camera. At each level of abstraction, properties of image processing applications are used along with structure composition to provide a generic architecture that can be automatically verified and mapped to the lower abstraction level. The result is a framework that encapsulates the computer vision library OpenCV at the highest level, integrates Accelera's System-C/TLM with UVM and QEMU-OS …

Enabling Runtime Self-Coordination Of Reconfigurable Embedded Smart Cameras In Distributed Networks, Franck Ulrich Yonga Yonga

Graduate Theses and Dissertations

Smart camera networks are real-time distributed embedded systems able to perform computer vision using multiple cameras. This new approach is a confluence of four major disciplines (computer vision, image sensors, embedded computing and sensor networks) and has been subject of intensive work in the past decades. The recent advances in computer vision and network communication, and the rapid growing in the field of high-performance computing, especially using reconfigurable devices, have enabled the design of more robust smart camera systems. Despite these advancements, the effectiveness of current networked vision systems (compared to their operating costs) is still disappointing; the main reason …

Technology Mapping, Design For Testability, And Circuit Optimizations For Null Convention Logic Based Architectures, Farhad Alibeygi Parsan

Graduate Theses and Dissertations

Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy consumption, less noise and EMI emission, and easy design reuse are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits.

This dissertation investigates new areas in NCL design and test and is made of three sections. The first section discusses …

Efficient Fpga Architectures For Separable Filters And Logarithmic Multipliers And Automation Of Fish Feature Extraction Using Gabor Filters, Arjun Kumar Joginipelly

LSU New Orleans Theses and Dissertations

Convolution and multiplication operations in the filtering process can be optimized by minimizing the resource utilization using Field Programmable Gate Arrays (FPGA) and separable filter kernels. An FPGA architecture for separable convolution is proposed to achieve reduction of on-chip resource utilization and external memory bandwidth for a given processing rate of the convolution unit.

Multiplication in integer number system can be optimized in terms of resources, operation time and power consumption by converting to logarithmic domain. To achieve this, a method altering the filter weights is proposed and implemented for error reduction. The results obtained depict significant error reduction when …

Idpal – A Partially-Adiabatic Energy-Efficient Logic Family: Theory And Applications To Secure Computing, Mihail T. Cutitaru

Electrical & Computer Engineering Theses & Dissertations

Low-power circuits and issues associated with them have gained a significant amount of attention in recent years due to the boom in portable electronic devices. Historically, low-power operation relied heavily on technology scaling and reduced operating voltage, however this trend has been slowing down recently due to the increased power density on chips. This dissertation introduces a new very-low power partially-adiabatic logic family called Input-Decoupled Partially-Adiabatic Logic (IDPAL) with applications in low-power circuits. Experimental results show that IDPAL reduces energy usage by 79% compared to equivalent CMOS implementations and by 25% when compared to the best adiabatic implementation. Experiments ranging …

Ad-Hoc Hid: Modular Wireless Human Interface Device, Joseph A. Mazzanti

Electrical Engineering

Ad-Hoc HID is a modular, reprogrammable Human Interface Device. This device is intended to function as a keyboard, gamepad, or mouse, according to the user's needs. The final project is intended to be switch agnostic, making the final product adaptable to the user’s needs.

Mos Current Mode Logic (Mcml) Analysis For Quiet Digital Circuitry And Creation Of A Standard Cell Library For Reducing The Development Time Of Mixed Signal Chips, David Marusiak

Master's Theses

Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with …

High-Speed Mobile Networks For Modern Farming And Agricultural Systems, Santos Najar

Master's Theses

ABSTRACT

High-Speed Mobile Networks for Modern Farming and Agricultural Systems

J.Santos Najar-Ramirez

High-speed mobile networks are necessary for agriculture to inventory individual plant health, maximize yield and minimize the resources applied. More specifically, real-time information on individual plant status is critical to decisions regarding the management of resources reserved and expended. This necessity can be met by the availability of environmental sensors (such as humidity, temperature, and pH) whose data is kept on storage servers connected to static and mobile local area networks. These static and mobile local area networks are connected to cellular, core and satellite networks. For …

Vehicular Motion Sensor: Developing A Wide-Range Motion Sensing Alarm System, Joshua Isaacson

Senior Honors Theses

Vehicular safety has become a serious concern in recent years. Many drivers have difficulty backing out of parking spaces, especially when large trucks and sport utility vehicles block the peripheral view from smaller vehicles. This can lead to accidents and pedestrian injuries when drivers are unable to see or do not pay careful attention to their surroundings.

Vehicular motion sensor systems can alert drivers of approaching obstacles when attempting to back out of parking spaces with limited visibility. This thesis aims to explain the limitations of current systems and the research conducted by the author to develop a prototype for …

An Ant-Based Sensor Measurement Data Gathering System, Bolun Zhang, Dimitrios Peroulis

The Summer Undergraduate Research Fellowship (SURF) Symposium

Large-scale industries involved with a great amount of sensor measurements in their work are facing many challenges in data collection. Sensors are not on the same network; therefore each measurement has to be managed separately. Gathering all the measurement data to one terminal could be difficult. Once a measurement is obtained, it takes significant amount of time to process the data.The approaches our group takes here is to build a giant ANT wireless network that holds all the sensors’ measurements. To be more specific, every sensor has an ANT chip set up on its side. Each ANT chip is as …

Cad Tool Design For Ncl And Mtncl Asynchronous Circuits, Vijay Mani Pillai

Graduate Theses and Dissertations

This thesis presents an implementation of a method developed to readily convert Boolean designs into an ultra-low power asynchronous design methodology called MTNCL, which combines multi-threshold CMOS (MTCMOS) with NULL Convention Logic (NCL) systems. MTNCL provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. The proposed tool utilizes industry-standard CAD tools. This research also presents an Automated Gate-Level Pipelining with Bit-Wise Completion (AGLPBW) method to maximize throughput of delay-insensitive full-word pipelined NCL circuits. These methods have been integrated into the Mentor Graphics and …

Analysis Of Parameter Tuning On Energy Efficiency In Asynchronous Circuits, Justin Thomas Roark

Graduate Theses and Dissertations

Power and energy consumption are the primary concern of the digital integrated circuit (IC) industry. Asynchronous logic, in the past several years, has increased in popularity due to its low power nature. This thesis analyzes a collection of array multipliers with different parameters to compare two asynchronous design paradigms, NULL Convention Logic (NCL) and Multi-Threshold NULL Convention Logic (MTNCL). Several commercially available pieces of software and custom scripts are used to analyze the asynchronous circuits and their components to provide the energy consumption estimation on various parts of each circuit. The analysis of the software results revealed that MTNCL circuits …

Cad Tools For Synthesis Of Sleep Convention Logic, Parviz Palangpour

Graduate Theses and Dissertations

This dissertation proposes an automated flow for the Sleep Convention Logic (SCL) asynchronous design style. The proposed flow synthesizes synchronous RTL into an SCL netlist. The flow utilizes commercial design tools, while supplementing missing functionality using custom tools. A method for determining the performance bottleneck in an SCL design is proposed. A constraint-driven method to increase the performance of linear SCL pipelines is proposed. Several enhancements to SCL are proposed, including techniques to reduce the number of registers and total sleep capacitance in an SCL design.

Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker

College of Engineering: Graduate Celebration Programs

As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. Although Static-Timing Analysis (STA) remains an excellent tool, current trends in process scaling have imposed significant difficulties to STA. As one of the promising solutions, Statistical static timing analysis (SSTA) has become the frontier research topic in recent years in combating such variation effects. This poster will be focusing on two aspects of SSTA and its applications in VLSI designs: (1) Statistical timing modeling and analysis; and (2) Architectural implementations of the atomic operations (max and add) using …

Independent Component Analysis Enhancements For Source Separation In Immersive Audio Environments, Yue Zhao

Theses and Dissertations--Electrical and Computer Engineering

In immersive audio environments with distributed microphones, Independent Component Analysis (ICA) can be applied to uncover signals from a mixture of other signals and noise, such as in a cocktail party recording. ICA algorithms have been developed for instantaneous source mixtures and convolutional source mixtures. While ICA for instantaneous mixtures works when no delays exist between the signals in each mixture, distributed microphone recordings typically result various delays of the signals over the recorded channels. The convolutive ICA algorithm should account for delays; however, it requires many parameters to be set and often has stability issues. This thesis introduces the …