Electronic Devices and Semiconductor Manufacturing Commons^™

Chatgpt As Metamorphosis Designer For The Future Of Artificial Intelligence (Ai): A Conceptual Investigation, Amarjit Kumar Singh (Library Assistant), Dr. Pankaj Mathur (Deputy Librarian)

Library Philosophy and Practice (e-journal)

Abstract

Purpose: The purpose of this research paper is to explore ChatGPT’s potential as an innovative designer tool for the future development of artificial intelligence. Specifically, this conceptual investigation aims to analyze ChatGPT’s capabilities as a tool for designing and developing near about human intelligent systems for futuristic used and developed in the field of Artificial Intelligence (AI). Also with the helps of this paper, researchers are analyzed the strengths and weaknesses of ChatGPT as a tool, and identify possible areas for improvement in its development and implementation. This investigation focused on the various features and functions of ChatGPT that …

Improving Noise Immunity And Efficiency Using High-Precision Iterative Codes, Sherzod Shukhratovich Atadjanov, Aziza Ahmadjanovna Tursunova

Bulletin of TUIT: Management and Communication Technologies

The article discusses the issues of ensuring noise immunity in digital broadcasting systems, shows the importance of the transition to the optimal code and the need to use it in the field of noiseless coding in various areas of telecommunication transmission and reception of digital signals. The previous algorithms and error-correcting coding methods based on the Gray code, which are used in multi-level digital broadcast modulation schemes to minimize the intensity of bit errors, are highlighted. A model of error-correcting coding by the Gray method and methods for estimating the probability of error for the Gray code are presented. Based …

On Improving Robustness Of Hardware Security Primitives And Resistance To Reverse Engineering Attacks, Vinay C. Patil

Doctoral Dissertations

The continued growth of information technology (IT) industry and proliferation of interconnected devices has aggravated the problem of ensuring security and necessitated the need for novel, robust solutions. Physically unclonable functions (PUFs) have emerged as promising secure hardware primitives that can utilize the disorder introduced during manufacturing process to generate unique keys. They can be utilized as \textit{lightweight} roots-of-trust for use in authentication and key generation systems. Unlike insecure non-volatile memory (NVM) based key storage systems, PUFs provide an advantage -- no party, including the manufacturer, should be able to replicate the physical disorder and thus, effectively clone the PUF. …

Malicious Hardware & Its Effects On Industry, Gustavo Perez

Computer Science and Computer Engineering Undergraduate Honors Theses

In recent years advancements have been made in computer hardware security to circumnavigate the threat of malicious hardware. Threats come in several forms during the development and overall life cycle of computer hardware and I aim to highlight those key points. I will illustrate the various ways in which attackers exploit flaws in a chip design, or how malicious parties take advantage of the many steps required to design and fabricate hardware. Due to these exploits, the industry and consumers have suffered damages in the form of financial loss, physical harm, breaches of personal data, and a multitude of other …

A Morphable Fpga Soft Processor Using Llvm Infrastructure Targeting Low-Power Application-Specific Embedded Systems, Ehsan Ali

Chulalongkorn University Theses and Dissertations (Chula ETD)

The reconfigurable computing (RC) aims to combine the flexibility of General-Purpose Processor (GPP) with performance of Application Specific Integrated Circuits (ASIC). There are several architectures proposed since RC's inception in 1960s, but all have failed to become mainstream. The main factor preventing RC to become common practice is its requirement for implementers of algorithms (programmers) to be familiar with hardware design. In RC, a hardened processor cooperates with a dynamic reconfigurable Hardware Accelerator (HA) which is implemented on Field-Programmable Gate Array (FPGA). The HA implements crucial software kernel on hardware to increase performance and its design demands digital circuit expertise. …

Prototyping A Capacitive Sensing Device For Gesture Recognition, Chenglong Lin

Computer Science and Computer Engineering Undergraduate Honors Theses

Capacitive sensing is a technology that can detect proximity and touch. It can also be utilized to measure position and acceleration of gesture motions. This technology has many applications, such as replacing mechanical buttons in a gaming device interface, detecting respiration rate without direct contact with the skin, and providing gesture sensing capability for rehabilitation devices. In this thesis, an approach to prototype a capacitive gesture sensing device using the Eagle PCB design software is demonstrated. In addition, this paper tested and evaluated the resulting prototype device, validating the effectiveness of the approach.

Investigating The Effect Of Detecting And Mitigating A Ring Oscillator-Based Hardware Trojan, Lakshmi Ramakrishnan

Electrical Engineering Theses and Dissertations

The outsourcing of the manufacturing process of integrated circuits to fabrications plants all over the world has exposed these chips to several security threats, especially at the hardware level. There have been instances of malicious circuitry, such as backdoors, being added to circuits without the knowledge of the chip designers or vendors. Such threats could be immensely powerful and dangerous against confidentiality, among other vulnerabilities.

Defense mechanisms against such attacks have been probed and defense techniques have been developed. But with the passage of time, attack techniques have improved immensely as well. From directly observing the inputs or outputs, adversaries …

Skybridge-3d-Cmos: A Fine-Grained Vertical 3d-Cmos Technology Paving New Direction For 3d Ic, Jiajun Shi

Doctoral Dissertations

2D CMOS integrated circuit (IC) technology scaling faces severe challenges that result from device scaling limitations, interconnect bottleneck that dominates power and performance, etc. 3D ICs with die-die and layer-layer stacking using Through Silicon Vias (TSVs) and Monolithic Inter-layer Vias (MIVs) have been explored in recent years to generate circuits with considerable interconnect saving for continuing technology scaling. However, these 3D IC technologies still rely on conventional 2D CMOS’s device, circuit and interconnect mindset showing only incremental benefits while adding new challenges reliability issues, robustness of power delivery network design and short-channel effects as technology node scaling. Skybridge-3D-CMOS (S3DC) is …

Skybridge: A New Nanoscale 3-D Computing Framework For Future Integrated Circuits, Mostafizur Rahman

Doctoral Dissertations

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, continuing the traditional way of scaling to sub-20nm technologies is proving to be very difficult as MOSFETs are reaching their fundamental performance limits [1] and interconnection bottleneck is dominating IC operational power and performance [2]. Migrating to 3-D, as a way to advance scaling, has been elusive due to inherent customization and manufacturing requirements in CMOS architecture that are incompatible with 3-D organization. Partial attempts with die-die [3] and layer-layer [4] stacking have their own limitations [5]. We …

Multiferroic Tunnel Junctions And Ferroelectric Control Of Magnetic State At Interface, Y. W. Yin, M. Raju, W. J. Hu, John D. Burton, Y.-M. Kim, A. Y. Borisevich, S. J. Pennycook, S. M. Yang, T. W. Noh, Alexei Gruverman, X. G. Li, Z. D. Zhang, Evgeny Y. Tsymbal, Qi Li

Alexei Gruverman Publications

As semiconductor devices reach ever smaller dimensions, the challenge of power dissipation and quantum effect place a serious limit on the future device scaling. Recently, a multiferroic tunnel junction (MFTJ) with a ferroelectric barrier sandwiched between two ferromagnetic electrodes has drawn enormous interest due to its potential applications not only in multi-level data storage but also in electric field controlled spintronics and nanoferronics. Here, we present our investigations on four-level resistance states, giant tunneling electroresistance (TER) due to interfacial magnetoelectric coupling, and ferroelectric control of spin polarized tunneling in MFTJs. Coexistence of large tunneling magnetoresistance and TER has been observed …

Mos Current Mode Logic (Mcml) Analysis For Quiet Digital Circuitry And Creation Of A Standard Cell Library For Reducing The Development Time Of Mixed Signal Chips, David Marusiak

Master's Theses

Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with …

Wireless Transmission Network : A Imagine, Radhey Shyam Meena Engineer, Neeraj Kumar Garg Asst.Prof

Radhey Shyam Meena

World cannot be imagined without electrical power. Generally the power is transmitted through transmission networks. This paper describes an original idea to eradicate the hazardous usage of electrical wires which involve lot of confusion in particularly organizing them. Imagine a future in which wireless power transfer is feasible: cell phones, household robots, mp3 players, laptop computers and other portable electronic devices capable of charging themselves without ever being plugged in freeing us from that final ubiquitous power wire. This paper includes the techniques of transmitting power without using wires with an efficiency of about 95% with non-radioactivemethods. In this paper …

Battery Energy Storage System In Solar Power Generation, Radhey Shyam Meena Er., Deepa Sharma

Radhey Shyam Meena

Grid-connected solar PV dramatically changes the load profile of an electric utility customer. The expected widespread adoption of solar generation by customers on the distribution system poses significant challenges to system operators both in transient and steady state operation, from issues including voltage swings, sudden weather-induced changes in generation, and legacy protective devices designed with one-way power flow in mind

Battery Energy Storage System In Solar Power Generation, Radhey Shyam Meena Er.

Radhey Shyam Meena

As solar photovoltaic power generation becomes more commonplace, the inherent intermittency of the solar resource poses one of the great challenges to those who would design and implement the next generation smart grid. Specifically, grid-tied solar power generation is a distributed resource whose output can change extremely rapidly, resulting in many issues for the distribution system operator with a large quantity of installed photovoltaic devices. Battery energy storage systems are increasingly being used to help integrate solar power into the grid. These systems are capable of absorbing and delivering both real and reactive power with sub-second response times. With these …

Switch Yard Operation In Thermal Power Plant(Katpp Jhalawar Rajasthan), Radhey Shyam Meena Er.

Radhey Shyam Meena

Switchyard Provides the facilities for switching ,protection & Control of electric power. To handle high Voltage power with proper Safety measures. To isolate the noises coming from the grid with true 50Hz power SWITCH YARD IS IMPORTANT PART IN THERMAL PLANT. IN KALISINDH THERMAL 400KV AND 220KV SWITCH YARD LOCATED.

Full Custom Vlsi Design Of On-Line Stability Checkers, Chris Y. Lee

Master's Theses

A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.

A method for concurrent fault testing called On-line Stability Checking …

Project 308: Augmented Reality Mario Kart, Joseph Abad, David Allender, Joryl Calizo, Ryan Gaspar, Gavin Lee

Computer Engineering

Mario Kart is a popular go-kart racing game developed by Nintendo. The premise of the game is simple: drive a go-kart along a racetrack and reach the finish line before the other players. What makes this game unique, however, is the inclusion of weapons, traps, and other projectiles that a player can use to gain an advantage in the race. We have taken on the challenge of not only recreating this amazing game, but using the art of Augmented Reality to fully immerse the player in the full experience. Rather than play the game on a television screen with a …

Programmable Household Led Light Fixture, Jordan Locano

Electrical Engineering

This report details the development and construction of a LED light fixture to be used for household lighting. This document details background information, design ideas, project specifications, production, assembly, testing, and conclusions involved with this project. The goals of this project is to design and build a cost-effective replacement for traditional room lighting that can perform better and last longer than traditional methods.

High Power Microwave (Hpm) And Ionizing Radiation Effects On Cmos Devices, Nicholas A. Estep

Theses and Dissertations

Integrated circuits (ICs) are inherently complicated and made worse by increasing transistor quantity and density. This trend potentially enhances concomitant effects of high energy radiation and local or impressed electromagnetic interference (EMI). The reduced margin for signal error may counter any gain in radiation hardness from smaller device dimensions. Isolated EMI and ionizing radiation studies on circuits have been conducted extensively over the past 30 years. However, little focus has been placed on the combined effects. To investigate the effect of combined EMI and ionizing radiation, two complementary metal oxide semiconductor (CMOS) inverter technologies (CD4069 and SN74AUC1G04) were analyzed for …