Electrical and Computer Engineering Commons^™

Optimization Techniques For Machine Learning Inference And Near Memory Image Processing In Hardware For Highly Constrained Iot Edge Nodes, Rajeev Joshi

USF Tampa Graduate Theses and Dissertations

The growing demand for fast and energy-efficient hardware for resource-constrained Internet of Things (IoT) edge devices has highlighted the limitations of conventional computing architectures. This research focuses on addressing the demand for fast, optimized, and energy-efficient machine learning inference engines as well as image processing in IoT edge applications. In this work, we address three challenging research problems and devise efficient solutions. Our investigation involved comprehensive exploration and analysis, leading to the proposal of effective approaches for overcoming these demanding issues. Through our work, we contribute novel solutions that offer improved efficiency and effectiveness in handling these research problems.

First, …

Development Of Attack Resistant Cybersecurity Framework For Digital Health Systems, Sridevi A

Theses and Dissertations

The emerging cyber landscape demands the data to be protected by CIA triad which comprises Confidentiality, Integrity and Availability(CIA). For the swift diagnosis process, a standard patient data representation in the form of EHR (Electronic Health Record) plays a significant role. There exists a necessity to protect this EHR through the information security mechanisms namely encryption, watermarking and intrusion detection system for ensuring application and network layer security. Implementation of medical data protection solution on a reconfigurable hardware platform can further strengthen EHR security. This research work effectively achieves the CIA triad for healthcare cybersecurity at data, application and network …

Range-Doppler Map Processing Chain For Marine Radar On Fpga Of An Rfsoc, Nickolas W. Ogilvie

Master's Theses

To improve the accuracy and resolution of the measurements, radar systems employ increasingly complex, resource-intensive signal processing, larger bandwidths, and higher carrier frequencies. However, implementing these improvements requires more expensive, complex electronics that are larger and use more power. Using RFSoC (Radio Frequency System on Chips) in radars can address these challenges. By combining processors, an FPGA (Field Programmable Gate Array), and RF data converters into a single integrated circuit, RFSoCs allow for radar electronics that are physically smaller, use less power, and are simpler to design. As using RFSoCs to perform RF data conversion for radars has been already …

Neural Compression Inference Accelerator: A Cost And Energy-Effective Alternative To Conventional Machine Learning Inference Methods, Matthew Wallace

Master's Theses

Recent developments in machine learning and artificial intelligence have sparked an influx of workloads that require specialized computer hardware for cloud services. The hardware running machine learning models predominantly consists of graphics processing units (GPUs) and tensor processing units (TPUs). However, these com- ponents are expensive for cloud services to purchase, costly for customers to rent, prone to price spikes, and energy-intensive. In this research we show that both cloud services and customers would benefit from utilizing field programmable gate arrays (FPGAs) to alleviate the aforementioned challenges. An FPGA can be configured as a machine learning accelerator, operating similarly to …

A Reconfigurable Architecture For Matrix Multiplication For Low Power Applications, Jeffrey Love

Electrical and Computer Engineering ETDs

This thesis presents a hardware architecture for performing matrix multiplication via a systolic array to reduce time complexity and power consumption. The proposed architecture, the Neural Network Accelerator (NNA), was designed in Verilog HDL to perform 8-bit multiplication to reduce the resources required to implement the NNA on low-power FPGAs. The NNA’s open architecture is designed to support radiation test for fault tolerant designs targeting space applications. Commercial hardware architecture information is not public knowledge, which led us to build our own matrix multiplication architecture so that we could later study its feasibility for space applications.

The NNA was compared …

Approximate Computing Based Processing Of Mea Signals On Fpga, Mohammad Emad Hassan

Dissertations

The Microelectrode Array (MEA) is a collection of parallel electrodes that may measure the extracellular potential of nearby neurons. It is a crucial tool in neuroscience for researching the structure, operation, and behavior of neural networks. Using sophisticated signal processing techniques and architectural templates, the task of processing and evaluating the data streams obtained from MEAs is a computationally demanding one that needs time and parallel processing.
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/="/">This thesis proposes enhancing the capability of MEA signal processing systems by using approximate computing-based algorithms. These algorithms can be implemented in systems that process parallel MEA channels using the Field …

Soc Reconfigurable Architecture For Software-Trained Neural Networks On Fpga, Michael Wasef

Boise State University Theses and Dissertations

Neural networks are extensively used in software and hardware applications. In hardware applications, it is necessary to implement a small, accelerated, and configurable hardware architecture to be easily embedded in hardware devices to implement and execute the required neural network with superior performance. Such configurable hardware architecture allows the user to implement neural networks with different structures and easily modify or change them as needed.

In this dissertation, three architectures, each containing three layers, have been designed using a system-on-chip approach and implemented on a Field Programmable Gate Array (FPGA), to realize and accelerate the performance of three types of …

Design And Implementation Of A Low Cost And Portable Tactile Stimulator, Coşkun Kazma, Vecdi̇ Emre Levent, Merve Çardak, Ni̇zametti̇n Aydin

Turkish Journal of Electrical Engineering and Computer Sciences

When central nervous system has a problem, somatic area I and II respond to stimulation differently. Therefore, it is possible to identify some of the central nervous diseases when somatosensory on the fingertip is stimulated and responses are recorded and analyzed. We designed a system to stimulate the mechanoreceptors on fingertips. It is composed of a mechanical system for fingertip stimulation, an embedded controller, a control computer, and a software to control overall operation. During test, mechanoreceptors are stimulated according to the test protocols. Individuals' answers are recorded to be evaluated by the developed software. In this study, several design …

Networked Digital Predictive Control For Modular Dc-Dc Converters, Castulo Aaron De La O Pérez

Theses and Dissertations

The concept of power electronics building blocks (PEBB) has driven advancements in highly modularized converter systems with many identical subsystems. PEBBs are distributed subsets of converter systems and thus require communication with a control system for their coordination. For this type of system, the communication latency with hard deterministic deadlines is the driving attribute of communication system requirements. However, inherent communication requirements for PEBB-based converter systems also provide opportunities for coordination of energy flow.

Leveraging developments in Gigabit serial communication channels, a control and communication platform architecture for distributed control schemes based on the 2D-Torus communication network topology was developed …

Cmos Sensor Image-Acquisition And Image- Processing Control System Architecture, Haruka Kido

Electrical Engineering Student Publications

This report demonstrates an assessment of a PCAM camera module’s OV5640 CMOS sensor image-acquisition electrical circuit network system and hardware implementation for associated FPGA-modulated image-processing techniques using Digilent’s Zybo Z7-20 development board’s FPGA (Zynq 7000 SoC). By comparison between the control system architectures of 2 proposed Active Pixel CMOS sensor electrical network configurations (both 1 Row 1-Column Select Implementations) using electrical network transfer function derivations, time responses, Root Locus Plots, Bode Plots, and their system characteristics as preliminary analyses, FPGA-modulation of the CMOS sensor through image format adjustment is developed as an example of image properties adjustment enabled by the …

Real Time Simulation And Hardware In The Loop Methods For Power Electronics Power Distribution Systems, Michele Difronzo

Theses and Dissertations

System level testing of Power Electronics Power Distribution Systems (PEPDS) can be challenging when fine temporal resolution is required (time step below 100-200ns). In the recent years, our research group has proposed various methods to simulate in real-time PEPDS using FPGAs and time step as small as 50ns. While the proposed methods allow achieving the desired temporal resolution, they are extremely demanding in terms of resources usage and the size of the PEPDS that can be simulated on a single FPGA is strongly limited.

In this dissertation -work that takes as an example application the US Navy electric Ship Zonal …

Macromodeling And Accelerated Simulations Of Electric Machines, Ajay Pratap Yadav

Electrical Engineering Dissertations - Archive

Electric machines are the most important element in the power grid. Given its centennial legacy and the rise of electric vehicles and distributed energy resources, it is imperative to bring new technologies into this area. This work tries to bridge the gap between electric machines and innovative research domains such as convex optimization and FPGA-based hardware acceleration. Problems of electric machine parameter identification and real-time simulation are considered. A convex optimization-based framework is designed to identify machine parameters. This tool is used to perform the macromodeling of a synchronous machine from its magnetic-equivalent circuit model. Furthermore, it is used to …

Bibliometric Review Of Fpga Based Implementation Of Cnn, Priti Shahane, Piyush Tyagi, Purba Saha, Shravan Sainath, Swanand Bedekar

Library Philosophy and Practice (e-journal)

Nowadays Convolution Neural Network (CNN) has become the state of the art for machine learning algorithms due to their high accuracy. However, implementation of CNN algorithms on hardware platforms becomes challenging due to high computation complexity, memory bandwidth and power consumption. Hardware accelerators such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC) are suitable platforms to model CNN algorithms. Recently FPGAs have been considered as an attractive platform for CNN implementation. Modern FPGAs have various embedded hardware and software blocks such as a soft processor, DSP slice and memory blocks. These embedded resources …

Shift Register Puf Implementation On An Fpga, Sriram Thotakura

Electrical and Computer Engineering ETDs

In this thesis, a novel shift register-based physical unclonable function (PUF), called SRP, is proposed. The PUF is implemented on an FPGA and leverages the internal delay variations introduced by within-die process variations that occur within the Look-up tables (LUTs), routing and switches of the FPGA. PUFs are designed to generate bitstrings and keys on-the-fly that are device-specific (unique), random and reproducible. PUFs eliminate the need for a specialized (secure) non-volatile memory(NVM) to store the secret keys. This reduces the total cost of chips and systems, particularly those used in the Internet of Things, where it is common for systems …

Side Channel Attack Counter Measure Using A Moving Target Architecture, Jithin Joseph

Electrical and Computer Engineering ETDs

A novel countermeasure to side-channel power analysis attacks called Side-channel Power analysis Resistance for Encryption Algorithms using DPR or SPREAD is investigated in this thesis. The countermeasure leverages a strategy that is best characterized as a moving target architecture. Modern field programmable gate arrays (FPGA) architectures provide support for dynamic partial reconfiguration (DPR), a feature that allows real-time reconfiguration of the programmable logic (PL). The moving target architecture proposed in this work leverages DPR to implement a power analysis countermeasure to side-channel attacks, the most common of which are referred to as differential power analysis (DPA) and correlation power analysis …

Fpga-Based Scalable Road Image Stochastic Denosing Approach, Cheolhyeong Park, Kyung Ki Kim, Yong Bin Kim, Minsu Choi

Electrical and Computer Engineering Faculty Research & Creative Works

This work proposes FPGA-based stochastic computing for efficient and scalable road image stochastic denoising. Stochastic number generators were compared for fields requiring data reliability such as automotive vehicles. The denoising performance of PRNG (Pseudo-Random Number Generator) and LDSG (Low Discrepancy Sequence Generator) are showed in noised KETTI dataset with filtering algorithms. The proposed approach is expected to be easily applied to SoCs with embedded FPGA for lightweight embedded implementation of image denoising algorithms.

Neural Networks On An Fpga And The Exploration Of Hardware Friendly Activation Functions, Jiong Si, Sarah L. Harris, Evangelos Yfantis

Electrical & Computer Engineering Faculty Research

This paper describes our implementation of several neural networks built on a field programmable gate array (FPGA) and used to recognize a handwritten digit dataset—the Modified National Institute of Standards and Technology (MNIST) database. We also propose a novel hardware-friendly activation function called the dynamic Rectifid Linear Unit (ReLU)—D-ReLU function that achieves higher performance than traditional activation functions at no cost to accuracy. We built a 2-layer online training multilayer perceptron (MLP) neural network on an FPGA with varying data width. Reducing the data width from 8 to 4 bits only reduces prediction accuracy by 11%, but the FPGA area …

Hardware Development For The Generation Of Large-Volume High Pressure Plasma By Spatiotemporal Control Of Space Charge, Nikhil Boothpur

Electrical & Computer Engineering Theses & Dissertations

While generating a plasma under laboratory conditions, any attempt to scale the pressure and volume leads to instabilities due to the build-up of localized space-charge. This poses a challenge in the design of the discharge chamber, type of excitation field, and the type of gas that is used in the discharge. This work investigates a spatially and temporally varying electric field to control the formation of space-charge in large-volume (greater than 5 mm in the smallest dimension) near atmospheric pressure. The simulations show that in a space-charge dominated transport, the charged species disperse both in azimuthal and radial directions in …

End-To-End Direct Digital Synthesis Simulation And Mathematical Model To Minimize Quantization Effects Of Digital Signal Generation, Pranav R. Patel, Richard K. Martin

Faculty Publications

Direct digital synthesis (DDS) architectures are becoming more prevalent as modern digital-to-analog converter (DAC) and programmable logic devices evolve to support higher bandwidths. The DDS architecture provides the benefit of digital control but at a cost of generating spurious content in the spectrum. The generated spurious content may cause intermodulation distortion preventing proper demodulation of the received signal. The distortion may also interfere with the neighboring frequency bands. This article presents the various DDS architectures and explores the DDS architecture which provides the most digital reconfigurability with the lowest spurious content. End-to-end analytical equations, numerical and mathematical models are developed …

Data Processing Electronics For An Ultra-Fast Single-Photon Counting Camera, Jackson Hyde

McKelvey School of Engineering Graduate Student Theses & Dissertations

Localizing photon arrivals with high spatial (megapixel) and temporal (sub-nanosecond) resolution would be transformative for a number of applications, including single-molecule super-resolution fluorescence microscopy. Here, the Data Processing Field Programmable Gate Array (FPGA) is developed as an ultra-fast computational platform built on an FPGA for a microchannel plate (MCP)-photomultiplier tube (PMT) based single-photon counting camera. Each photon is converted by the MCP-PMT into an electron cloud that generates current pulses across a 50×50 cross-strip anode. The Data Processing FPGA executes a massively parallel center-of-gravity coordinate determination algorithm on the digitized current pulses to determine a 2D position and time of …

Medusa: A Low-Cost, 16-Channel Neuromodulation Platform With Arbitrary Waveform Generation, Fnu Tala, Benjamin C. Johnson

Electrical and Computer Engineering Faculty Publications and Presentations

Neural stimulation systems are used to modulate electrically excitable tissue to interrogate neural circuit function or provide therapeutic benefit. Conventional stimulation systems are expensive and limited in functionality to standard stimulation waveforms, and they are bad for high frequency stimulation. We present MEDUSA, a system that enables new research applications that can leverage multi-channel, arbitrary stimulation waveforms. MEDUSA is low cost and uses commercially available components for widespread adoption. MEDUSA is comprised of a PC interface, an FPGA for precise timing control, and eight bipolar current sources that can each address up to 16 electrodes. The current sources have a …

An Fpga-Based Hardware Accelerator For The Digital Image Correlation Engine, Keaten Stokke

Graduate Theses and Dissertations

The work presented in this thesis was aimed at the development of a hardware accelerator for the Digital Image Correlation engine (DICe) and compare two methods of data access, USB and Ethernet. The original DICe software package was created by Sandia National Laboratories and is written in C++. The software runs on any typical workstation PC and performs image correlation on available frame data produced by a camera. When DICe is introduced to a high volume of frames, the correlation time is on the order of days. The time to process and analyze data with DICe becomes a concern when …

Performance Investigation Of Peak Shrinking And Interpolating The Papr Reduction Technique For Lte-Advance And 5g Signals, Somayeh Mohammady, Ronan Farrell, David Malone, John Dooley

Articles

Orthogonal frequency division multiplexing (OFDM) has become an indispensable part of waveform generation in wideband digital communication since its first appearance in digital audio broadcasting (DAB) in Europe in 1980s, and it is indeed in use. As has been seen, the OFDM based waveforms work well with time division duplex operation in new radio (NR) systems in 5G systems, supporting delay-sensitive applications, high spectral efficiency, massive multiple input multiple output (MIMO) compatibility, and ever-larger bandwidth signals, which has demonstrated successful commercial implementation for 5G downlinks and uplinks up to 256-QAM modulation schemes. However, the OFDM waveforms suffer from high peak …

Neural Network In Hardware, Jiong Si

UNLV Theses, Dissertations, Professional Papers, and Capstones

This dissertation describes the implementation of several neural networks built on a field programmable gate array (FPGA) and used to recognize a handwritten digit dataset – the Modified National Institute of Standards and Technology (MNIST) database. A novel hardwarefriendly activation function called the dynamic ReLU (D-ReLU) function is proposed. This activation function can decrease chip area and power of neural networks when compared to traditional activation functions at no cost to prediction accuracy.

The implementations of three neural networks on FPGA are presented: 2-layer online training fully-connected neural network, 3-layer offline training fully-connected neural network, and two solutions of Super-Skinny …

Adaptive-Hybrid Redundancy For Radiation Hardening, Nicolas S. Hamilton

Theses and Dissertations

An Adaptive-Hybrid Redundancy (AHR) mitigation strategy is proposed to mitigate the effects of Single Event Upset (SEU) and Single Event Transient (SET) radiation effects. AHR is adaptive because it switches between Triple Modular Redundancy (TMR) and Temporal Software Redundancy (TSR). AHR is hybrid because it uses hardware and software redundancy. AHR is demonstrated to run faster than TSR and use less energy than TMR. Furthermore, AHR allows space vehicle designers, mission planners, and operators the flexibility to determine how much time is spent in TMR and TSR. TMR mode provides faster processing at the expense of greater energy usage. TSR …

Statistical Analysis Of A Channel Emulator For Noisy Gradient Descent Low Density Parity Check Decoder, Rakin Muhammad Shadab

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

The purpose of a channel emulator is to emulate a communication channel in real-life use case scenario. These emulators are often used in the domains of research in digital and wireless communication. One such area is error correction coding, where transmitted data bits over a channel are decoded and corrected to prevent data loss. A channel emulator that does not follow the properties of the channel it is intended to replicate can lead to mistakes while analyzing the performance of an error-correcting decoder. Hence, it is crucial to validate an emulator for a particular communication channel. This work delves into …

Improving The Single Event Effect Response Of Triple Modular Redundancy On Sram Fpgas Through Placement And Routing, Matthew Joel Cannon

Theses and Dissertations

Triple modular redundancy (TMR) with repair is commonly used to improve the reliability of systems. TMR is often employed for circuits implemented on field programmable gate arrays (FPGAs) to mitigate the radiation effects of single event upsets (SEUs). This has proven to be an effective technique by improving a circuit's sensitive cross-section by up to 100x. However, testing has shown that the improvement offered by TMR is limited by upsets in single configuration bits that cause TMR to fail.This work proposes a variety of mitigation techniques that improve the effectiveness of TMR on FPGAs. These mitigation techniques can alter the …

Optimization And Hardware Implementation Of Syba-An Efficient Feature Descriptor, Samuel Gaylin Fuller

Theses and Dissertations

Feature detection, description and matching are crucial steps in many computer vision algorithms. These rely on feature descriptors to be able to match image features across sets of images. This paper discusses a hardware implementation and various optimizations of our lab's previous work on the SYnthetic BAsis feature descriptor (SYBA). Previous work has shown that SYBA can offer superior performance to other binary descriptors, such as BRIEF. This hardware implementation on an FPGA is a high throughput and low latency solution, which is critical for applications such as: high speed object detection and tracking, stereo vision, visual odometry, structure from …

Surface Engineering Solutions For Immersion Phase Change Cooling Of Electronics, Brendon M. Doran

Master's Theses

Micro- and nano-scale surface modifications have been a subject of great interest for enhancing the pool boiling heat transfer performance of immersion cooling systems due to their ability to augment surface area, improve wickability, and increase nucleation site density. However, many of the surface modification technologies that have been previously demonstrated show a lack of evidence concerning scalability for use at an industrial level. In this work, the pool boiling heat transfer performance of nanoporous anodic aluminum oxide (AAO) films, copper oxide (CuO) nanostructure coatings, and 1D roll-molded microfin arrays has been studied. Each of these technologies possess scalability in …

Integration And Validation Of Power Hardware-In-The-Loop Generator Models For Deployment In A Distributed Generation Source Testbed, Jacob Sanchez

Electrical Engineering Dissertations - Archive

Hardware in the Loop (HIL) is an established technology that allows for rapid prototyping of controls and verification of how physical devices respond for valid simulated systems. This involves deploying a model of a system onto a Field Programmable Gate Array (FPGA) that can take in external inputs and outputs the state variables present in the system. An example of this could involve the control of the roll, pitch, and yaw of a plane. A simulated plane could output the current state variables of the plane to an external controller which will respond with control signals to the simulated system …