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FPGA

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Articles 151 - 180 of 181

Full-Text Articles in Electrical and Computer Engineering

Vector Support For Multicore Processors With Major Emphasis On Configurable Multiprocessors, Hongyan Yang May 2008

Vector Support For Multicore Processors With Major Emphasis On Configurable Multiprocessors, Hongyan Yang

Dissertations

It recently became increasingly difficult to build higher speed uniprocessor chips because of performance degradation and high power consumption. The quadratically increasing circuit complexity forbade the exploration of more instruction-level parallelism (JLP). To continue raising the performance, processor designers then focused on thread-level parallelism (TLP) to realize a new architecture design paradigm. Multicore processor design is the result of this trend. It has proven quite capable in performance increase and provides new opportunities in power management and system scalability. But current multicore processors do not provide powerful vector architecture support which could yield significant speedups for array operations while maintaining …

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Real-Time Implementation Of Vision Algorithm For Control, Stabilization, And Target Tracking For A Hovering Micro-Uav, Beau J. Tippetts Apr 2008

Real-Time Implementation Of Vision Algorithm For Control, Stabilization, And Target Tracking For A Hovering Micro-Uav, Beau J. Tippetts

Theses and Dissertations

A lightweight, powerful, yet efficient quad-rotor platform was designed and constructed to obtain experimental results of completely autonomous control of a hovering micro-UAV using a complete on-board vision system. The on-board vision and control system is composed of a Helios FPGA board, an Autonomous Vehicle Toolkit daughterboard, and a Kestrel Autopilot. The resulting platform is referred to as the Helio-copter. An efficient algorithm to detect, correlate, and track features in a scene and estimate attitude information was implemented with a combination of hardware and software on the FPGA, and real-time performance was obtained. The algorithms implemented include a Harris feature …

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Stabilization And Control Of A Quad-Rotor Micro-Uav Using Vision Sensors, Spencer G. Fowers Apr 2008

Stabilization And Control Of A Quad-Rotor Micro-Uav Using Vision Sensors, Spencer G. Fowers

Theses and Dissertations

Quad-rotor micro-UAVs have become an important tool in the field of indoor UAV research. Indoor flight poses problems not experienced in outdoor applications. The ability to be location- and movement-aware is paramount because of the close proximity of obstacles (walls, doorways, desks). The Helio-copter, an indoor quad-rotor platform that utilizes a compact FPGA board called Helios has been developed in the Robotic Vision Lab at Brigham Young University. Helios allows researchers to perform on-board vision processing and feature tracking without the aid of a ground station or wireless transmission. Using this on-board feature tracking system a drift stabilization control system …

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Fpga Design Of A Hardware Efficient Pipelined Fft Processor, Ryan T. Bone Jan 2008

Fpga Design Of A Hardware Efficient Pipelined Fft Processor, Ryan T. Bone

Browse all Theses and Dissertations

Digital receivers involve fast Fourier transform (FFT) computations that require a large amount of arithmetic operations. The implementation of a FFT processor is one of the most challenging parts in the realization of a wideband receiver and its hardware complexity is very high. Hence, kernel function FFT processors have been proposed to meet real-time processing requirements and to reduce hardware complexity by rounding the kernel function to predetermined kernel points so as to eliminate the multipliers and use only shifters and adders or subtractors. Because of the nonlinear nature of this approximation by the rounding errors, spurious responses are generated …

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High-Speed Data Acquisition And Fpga Detected Pulse Blanking System For Interference Mitigation In Radio Astronomy, Micah Alexander Lillrose Aug 2007

High-Speed Data Acquisition And Fpga Detected Pulse Blanking System For Interference Mitigation In Radio Astronomy, Micah Alexander Lillrose

Theses and Dissertations

Radio astronomy is the discipline dedicated to the study of celestial emissions in the radio band from a few MHz to 300 GHz. In recent years, spurious emissions from man-made devices that operate at these frequencies have made detection of astronomical signals difficult. These harmful RF transmissions are called radio frequency interference (RFI). One strategy to remove RFI is to apply spatial filtering using an array antenna. This thesis documents the development of a high-speed data acquisition system used to record data from 7- and 19-element phased array feeds. The system supports synchronous sampling over all channels and streams data …

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Hardware Support For A Configurable Architecture For Real-Time Embedded Systems On A Programmable Chip, Spencer W. Isaacson Jul 2007

Hardware Support For A Configurable Architecture For Real-Time Embedded Systems On A Programmable Chip, Spencer W. Isaacson

Theses and Dissertations

Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young University leverages the advances in FPGA technology with a system architecture that is customizable to specific applications. A simple real-time processor has been designed to provide support for a hardware-assisted real-time operating system providing fast context switches. As part of the hardware RTOS, the following have been implemented in hardware: scheduler, register banks, mutex, semaphore, queue, interrupts, event, and others. A novel circuit called the Task-Resource Matrix has been created to allow fast inter/intra processor …

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Compilation And Generation Of Multi-Processor On A Chip Real-Time Embedded Systems, Randall S. Klingler Jul 2007

Compilation And Generation Of Multi-Processor On A Chip Real-Time Embedded Systems, Randall S. Klingler

Theses and Dissertations

Current FPGA technology has advanced to the point that useful embedded System-on-Programmable-Chips (SoPC)s can now be designed. The Real Time Processor (RTP) project leverages the advances in FPGA technology with a system architecture that is customizable to specific real-time applications. The design and implementation of the framework for architecting such a system from ANSI-C code is presented. The Small Device C Compiler (SDCC) was retargeted to the RTP architecture and extended to produce a generator directive file. The RTPGen hardware generator was created to consume the directive file and produce a highly customized top-level structural VHDL file that can be …

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Reducing Power In Fpga Designs Through Glitch Reduction, Nathaniel Hatley Rollins Feb 2007

Reducing Power In Fpga Designs Through Glitch Reduction, Nathaniel Hatley Rollins

Theses and Dissertations

While FPGAs provide flexibility for performing high performance DSP functions, they consume a significant amount of power. Often, a large portion of the dynamic power is wasted on unproductive signal glitches. Reducing glitching reduces dynamic energy consumption. In this study, retiming is used to reduce the unproductive energy wasted in signal glitches. Retiming can reduce energy by up to 92%. Evaluating energy consumption is an important part of energy reduction. In this work, an activity rate-based power estimation tool is introduced to provide FPGA architecture independent energy estimations at the gate level. This tool can accurately estimate power consumption to …

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Power-Aware Design Methodologies For Fpga-Based Implementation Of Video Processing Systems, Hau Trung Ngo Jan 2007

Power-Aware Design Methodologies For Fpga-Based Implementation Of Video Processing Systems, Hau Trung Ngo

Electrical & Computer Engineering Theses & Dissertations

The increasing capacity and capabilities of FPGA devices in recent years provide an attractive option for performance-hungry applications in the image and video processing domain. FPGA devices are often used as implementation platforms for image and video processing algorithms for real-time applications due to their programmable structure that can exploit inherent spatial and temporal parallelism. While performance and area remain as two main design criteria, power consumption has become an important design goal especially for mobile devices. Reduction in power consumption can be achieved by reducing the supply voltage, capacitances, clock frequency and switching activities in a circuit. Switching activities …

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Improved Thresholding Technique For The Monobit Receiver, Jonathan Gordon Buck Jan 2007

Improved Thresholding Technique For The Monobit Receiver, Jonathan Gordon Buck

Browse all Theses and Dissertations

Wideband digital receivers typically use a very high sampling rate to capture a signal for near real-time processing. Very robust digital techniques, like the Monobit FFT technique, have been developed to provide near real-time processing of captured timedomain signals. Most of these techniques trade accuracy for processing speed by approximating computationally complex mathematical operations. The approximation sometimes makes it difficult to detect multiple signals if the difference between their amplitudes is more than a few dB. This thesis presents a dynamic thresholding technique for multi-tone signal detection. The technique is based on setting an allowable ratio between the magnitude of …

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Using Duplication With Compare For On-Line Error Detection In Fpga-Based Designs, Daniel L. Mcmurtrey Dec 2006

Using Duplication With Compare For On-Line Error Detection In Fpga-Based Designs, Daniel L. Mcmurtrey

Theses and Dissertations

Space destined FPGA-based systems must employ redundancy techniques to account for the effects of upsets caused by radiated environments. Error detection techniques can be used to alert external systems to the presence of these upsets. Readback with compare is an error detection technique commonly employed in FPGA-based designs. This work introduces duplication with compare (DWC) as an automated on-line error detection technique that can be used as an alternative to readback with compare. This work also introduces a set of metrics that is used to quantify the effectiveness and coverage of this error detection technique. A tool is presented that …

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Seu-Induced Persistent Error Propagation In Fpgas, Keith S. Morgan Jul 2006

Seu-Induced Persistent Error Propagation In Fpgas, Keith S. Morgan

Theses and Dissertations

This thesis introduces a new way to characterize the dynamic SEU cross section of an FPGA design in terms of its persistent and non-persistent components. An SEU in the persistent cross section results in a permanent interruption of service until reset. An SEU in the non-persistent cross section causes a temporary interruption of service, but in some cases this interruption may be tolerated. Techniques for measuring these cross sections are introduced. These cross sections can be measured and characterized for an arbitrary FPGA design. Furthermore, circuit components in the non-persistent and persistent cross section can statically be determined. Functional error …

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Active Fpga Security Through Decoy Circuits, Bradley D. Christiansen Jun 2006

Active Fpga Security Through Decoy Circuits, Bradley D. Christiansen

Theses and Dissertations

Field Programmable Gate Arrays (FPGAs) based on Static Random Access Memory (SRAM) are vulnerable to tampering attacks such as readback and cloning attacks. Such attacks enable the reverse engineering of the design programmed into an FPGA. To counter such attacks, measures that protect the design with low performance penalties should be employed. This research proposes a method which employs the addition of active decoy circuits to protect SRAM FPGAs from reverse engineering. The effects of the protection method on security, execution time, power consumption, and FPGA resource usage are quantified. The method significantly increases the security of the design with …

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Modeling Of The Ic's Switching Currents On The Power Bus Of A High Speed Digital Board, Mauro Lai, James L. Drewniak, Vittorio Ricchiuti, Antonio Orlandi, Giulio Antonini May 2006

Modeling Of The Ic's Switching Currents On The Power Bus Of A High Speed Digital Board, Mauro Lai, James L. Drewniak, Vittorio Ricchiuti, Antonio Orlandi, Giulio Antonini

Electrical and Computer Engineering Faculty Research & Creative Works

When the performances of the electronic technology increase (higher frequencies, more power, lover power supply, faster transistors, reduced chip dimensions), designing electronic equipment becomes more challenging for the electronic engineers. Signal and power integrity on board become of paramount importance. One of the main causes of board malfunctions and electromagnetic radiation is the simultaneous switching noise (SSN) due to the integrated circuits soldered on the board. The paper proposes two simple procedures to model the SSN, so to evaluate its effects in any point of the board.

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Fpga-Based Experiment Platform For Hardware-Software Codesign And Hardware Emulation, Yajuvendra Nagaonkar May 2006

Fpga-Based Experiment Platform For Hardware-Software Codesign And Hardware Emulation, Yajuvendra Nagaonkar

Theses and Dissertations

An FPGA-based experiment platform for hardware-software codesign experiments was developed. The proposed platform would be used by an engineer who can be affiliated with academia, research or industry for codesign experiments or hardware emulation. The platform utilizes a combination of a microcontroller and a FPGA device to enable sufficient flexibility in exploring the design space to implement codesign experiments. The FPGA device operation is integrated with that of the microcontroller to provide an overall embedded solution for codesign experimentations. It is anticipated that the platform will be used in academia for educating the students the concepts of computer architecture and …

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Pipelining Of Double Precision Floating Point Division And Square Root Operations On Field-Programmable Gate Arrays, Anuja Thakkar Jan 2006

Pipelining Of Double Precision Floating Point Division And Square Root Operations On Field-Programmable Gate Arrays, Anuja Thakkar

Electronic Theses and Dissertations

Many space applications, such as vision-based systems, synthetic aperture radar, and radar altimetry rely increasingly on high data rate DSP algorithms. These algorithms use double precision floating point arithmetic operations. While most DSP applications can be executed on DSP processors, the DSP numerical requirements of these new space applications surpass by far the numerical capabilities of many current DSP processors. Since the tradition in DSP processing has been to use fixed point number representation, only recently have DSP processors begun to incorporate floating point arithmetic units, even though most of these units handle only single precision floating point addition/subtraction, multiplication, …

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Fpga Frequency Domain Based Gps Coarse Acquisition Processor Using Fft, Cyprian D. Sajabi Jan 2006

Fpga Frequency Domain Based Gps Coarse Acquisition Processor Using Fft, Cyprian D. Sajabi

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The Global Positioning System or GPS is a satellite based technology that has gained widespread use worldwide in civilian and military applications. Direct Sequence Spread spectrum (DSSS) is the method whereby the data transmitted by the satellite and received by user is kept secure, low power and relatively noise-immune. The first step required in the GPS operation is to perform a lock on the incoming signal, both with respect to time synchronization and frequency resolution. Because of the need for reduced time to lock and also reduced hardware, algorithms based in the frequency domain have been developed. These algorithms take …

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Correlation Of Fault-Injection To Proton Accelerator Persistent Cross Section Measurements, Keith S. Morgan, Michael J. Wirthlin Jun 2005

Correlation Of Fault-Injection To Proton Accelerator Persistent Cross Section Measurements, Keith S. Morgan, Michael J. Wirthlin

Faculty Publications

Sponsorship: Los Alamos National Laboratory. Field Programmable Gate Arrays (FPGAs) are an attractive solution for space system electronics. Unfortunately, FPGAs are susceptible to radiation-induced single-event upsets (SEU). As such, the FPGA Reliability Studies research group (http://reliability.ee.byu.edu) at Brigham Young University has studied ways to effectively measure the static, dynamic and persistent cross sections of an FPGA desgin; each of which are characterized in some way by how the part reacts to an SEU. One such method is to actually radiate an FPGA and monitor how it reacts to SEUs. A cheaper, more efficient solution is to use fault-injection to emulate …

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Predicting On-Orbit Seu Rates, Keith S. Morgan, Michael J. Wirthlin Jun 2005

Predicting On-Orbit Seu Rates, Keith S. Morgan, Michael J. Wirthlin

Faculty Publications

As process geometry sizes continue to decrease, microelectronics are becoming more vulnerable to the effects of radiation. Of particular concern are the effects of Single-Event Upsets (SEU) in Field Programmable Gate Arrays (FPGA). An SEU causes a dynamic memory element, such as a flip-flop or latch, to unwantedly change state. Since FPGAs are becoming an increasingly attractive solution for space system electronics, it is desirable to predict static on-orbit SEU rates likely to be encountered by a particular device for any particular orbit. Mean Time Between Failure (MTBF) can directly be calculated from a static SEU rate, allowing a system …

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Higher Radix Floating-Point Representations For Fpga-Based Arithmetic, Bryan Christopher Catanzaro Apr 2005

Higher Radix Floating-Point Representations For Fpga-Based Arithmetic, Bryan Christopher Catanzaro

Theses and Dissertations

Field Programmable Gate Arrays (FPGAs) are increasingly being used for high-throughput floating-point computation. It is forecasted that by 2009, FPGAs will provide an order of magnitude greater sustained floating-point throughput than conventional processors. FPGA implementations of floating-point operators have historically been designed to use binary floating-point representations, as do general purpose processors. Binary representations were chosen as the standard over three decades ago because they provide maximal numerical accuracy per bit of floating-point data. However, the unique nature of FPGA-based computation makes numerical accuracy per unit of FPGA resources a more important measure of the usefulness of a given floating-point …

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Estimating The Dynamic Sensitive Cross Section Of An Fpga Design Through Fault Injection, Darrel E. Johnson Apr 2005

Estimating The Dynamic Sensitive Cross Section Of An Fpga Design Through Fault Injection, Darrel E. Johnson

Theses and Dissertations

A fault injection tool has been created to emulate single event upset (SEU) behavior within the configuration memory of an FPGA. This tool is able to rapidly and accurately determine the dynamic sensitive cross section of the configuration memory for a given FPGA design. This tool enables the reliability of FPGA designs and fault tolerance schemes to be quickly and accurately tested. The validity of testing performed with this fault injection tool has been confirmed through radiation testing. A radiation test was conducted at Crocker Nuclear Laboratory using a proton accelerator in order to determine the actual dynamic sensitive cross …

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A Flexible Circuit-Switched Communication Network For Fpga-Based Soc Design, Clint Richard Hilton Apr 2005

A Flexible Circuit-Switched Communication Network For Fpga-Based Soc Design, Clint Richard Hilton

Theses and Dissertations

As FPGA densities continue to improve, single chips are becoming capable of implementing larger and more complex systems. Even today these systems may include several processors working in conjuction with a handful of other standard interfaces or custom modules. Additional system complexity naturally leads to added complexity throughout the different design and implementation stages. Attempting to design such a system while maintaining high performance and within a reasonable time frame is becoming more and more difficult. Architectural design approaches ranging from direct module interconnection to sophisticated bus schemes have been used to build such systems, all with their own trade-offs. …

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Reducing Energy In Fpga Multipliers Through Glitch Reduction, Nathaniel Rollins, Michael J. Wirthlin Apr 2005

Reducing Energy In Fpga Multipliers Through Glitch Reduction, Nathaniel Rollins, Michael J. Wirthlin

Faculty Publications

Sponsorship: NASA Earth Science Technology Office (ESTO). While FPGAs provide exibility for performing high-performance DSP functions, they consume a significant amount of power. For arithmetic circuits, a large portion of the dynamic power is wasted on unproductive signal glitches. Pipelining can be used to significantly reduce the unproductive power wasted in signal glitches. This paper presents a methodology for estimating the amount of power consumed by glitches and applies this methodology to non-pipelined, pipelined, and digit-serial multipliers. This glitch estimation is used to evaluate these multipliers using four energy metrics: energy per operation, energy delay, energy throughput, and energy density. …

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Source Level Debugging Of Circuits Synthesized From High Level Language Descriptions, Karl S. Hemmert Apr 2004

Source Level Debugging Of Circuits Synthesized From High Level Language Descriptions, Karl S. Hemmert

Theses and Dissertations

The rapid increase in the density of modern FPGAs has allowed ever increasingly complex designs to be mapped to FPGAs. However, this increase in logic resources is accompanied by an increase in the complexity of describing and verifying the operation of an application. This has prompted the search for new approaches to the design, debug and verification of circuits. The desire to find more effecient approaches to designing these large FPGA circuits has led to the creation of synthesizing compilers that can create hardware from high-level descriptions based on general purpose programming languages. Being able to describe the application at …

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Analysis Of Chip-Level Emi Using Near-Field Magnetic Scanning, Xiaopeng Dong, Shaowei Deng, Todd H. Hubing, Daryl G. Beetner Jan 2004

Analysis Of Chip-Level Emi Using Near-Field Magnetic Scanning, Xiaopeng Dong, Shaowei Deng, Todd H. Hubing, Daryl G. Beetner

Electrical and Computer Engineering Faculty Research & Creative Works

Integrated circuits (ICs) are often a significant source of radiated energy from electronic systems. Well designed ICs maintain good control of the currents that they generate. However, poorly designed ICs can drive high-frequency noise currents onto nominally low-frequency input and output pins. These currents can excite unintentional radiating structures on the printed circuit board, resulting in radiated emissions that are difficult or expensive to control. The paper discusses the use of magnetic near-field scanning techniques to measure the current distribution in IC packages. This technique is applied to common ICs, including a clock driver, a memory module and a field …

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Fpga Placement And Routing Using Particle Swarm Optimization, Ganesh K. Venayagamoorthy, Venu Gopal Gudise Jan 2004

Fpga Placement And Routing Using Particle Swarm Optimization, Ganesh K. Venayagamoorthy, Venu Gopal Gudise

Electrical and Computer Engineering Faculty Research & Creative Works

Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. One of the necessary requirements to effectively utilize the FPGA's fixed resources is an efficient placement and routing mechanism. This paper presents particle swarm optimization (PSO) for FPGA placement and routing. Preliminary results for the implementation of an arithmetic logic unit on a Xilinx FPGA show that PSO is a potential technique for solving the placement and routing problem.

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Fpga-Based Design Of A Maximum-Power-Point Tracking System For Space A, Todd Persen Jan 2004

Fpga-Based Design Of A Maximum-Power-Point Tracking System For Space A, Todd Persen

Electronic Theses and Dissertations

Satellites need a source of power throughout their missions to help them remain operational for several years. The power supplies of these satellites, provided primarily by solar arrays, must have high efficiencies and low weights in order to meet stringent design constraints. Power conversion from these arrays is required to provide robust and reliable conversion which performs optimally in varying conditions of peak power, solar flux, and occlusion conditions. Since the role of these arrays is to deliver power, one of the principle factors in achieving maximum power output from an array is tracking and holding its maximum-power point. This …

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Designing, Debugging, And Deploying Configurable Computing Machine-Based Applications Using Reconfigurable Computing Application Frameworks, Anthony Lynn Slade Mar 2003

Designing, Debugging, And Deploying Configurable Computing Machine-Based Applications Using Reconfigurable Computing Application Frameworks, Anthony Lynn Slade

Theses and Dissertations

Configurable computing machines (CCMs) offer high-performance application acceleration with custom hardware. They are also dynamically reconfigurable and give significant internal visibility. Such features are useful throughout the design, debug, and deploy stages of CCM-based application development. However traditional, monolithic design tools do not offer adequate support for all of these development stages. This thesis describes a specification for a reconfigurable computing application framework (RCAF) which is more suitable for CCM application development. It also describes an implementation of such an RCAF. This RCAF improves the efficiency of application design and debugging. It also establishes an application architecture framework which helps …

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Logic Foundry: Rapid Prototyping For Fpga-Based Dsp Systems, Gary Spivey Jan 2003

Logic Foundry: Rapid Prototyping For Fpga-Based Dsp Systems, Gary Spivey

Faculty Publications - Department of Electrical Engineering and Computer Science

We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.

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Quality Enhancement Of Reconfigurable Multichip Module Systems By Redundancy Utilization, Minsu Choi, Nohpill Park, Fabrizio Lombardi, Vincenzo Piuri Aug 2002

Quality Enhancement Of Reconfigurable Multichip Module Systems By Redundancy Utilization, Minsu Choi, Nohpill Park, Fabrizio Lombardi, Vincenzo Piuri

Electrical and Computer Engineering Faculty Research & Creative Works

This paper evaluates the quality effectiveness of redundancy utilization in reconfigurable multichip mode (RMCM) systems. Due to reconfigurability, the RMCM system can implement a device with different redundancy levels. A redundancy level is determined by the requirement of fault tolerance (FT) of the device under implementation which can be realized through reconfiguration. No previous work has adequately investigated the effect of utilization of redundancy on the quality-level (QL) of RMCM. In this paper, the tolerance to escape from testing is also introduced to provide more extensive and comprehensive analysis and is referred to as escape tolerance (ET). This can be …

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