Electrical and Computer Engineering Commons^™

Understanding Design Requirements For Building Reliable, Space-Based Fpga Mgt Systems Based On Radiation Test Results, Kevin M. Ellsworth

Theses and Dissertations

Space-based computing applications often demand reliable, high-bandwidth communication systems. FPGAs with Mulit-Gigabit Transceivers (MGTs) provide an effective platform for such systems, but it is important that system designers understand the possible susceptibilities MGTs present to the system. Previous work has provided a foundation for understanding the susceptibility of raw FPGA MGTs but has fallen short of testing MGTs as part of a larger system. This work focuses on answering the questions MGT system designers need to know in order to build a reliable space-based MGT system. Two radiation tests were performed with a test architecture built on the Aurora protocol. …

Hardware And Software Fault-Tolerance Of Softcore Processors Implemented In Sram-Based Fpgas, Nathaniel Hatley Rollins

Theses and Dissertations

Softcore processors are an attractive alternative to using expensive radiation-hardened processors for space-based applications. Since they can be implemented in the latest SRAM-based FPGA technologies, they are fast, flexible and significantly less expensive. However, unlike ASIC-based processors, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). To protect softcore processors from SEUs, this dissertation explores the processor design-space for the LEON3 softcore processor implemented in a commercial SRAM-based FPGA. The traditional mitigation techniques of triple modular redundancy (TMR) and duplication with compare (DWC) and checkpointing provide reliability to a softcore processor at …

Using Hard Macros To Accelerate Fpga Compilation For Xilinx Fpgas, Christopher Michael Lavin

Theses and Dissertations

Field programmable gate arrays (FPGAs) offer an attractive compute platform because of their highly parallel and customizable nature in addition to the potential of being reconfigurable to any almost any desired circuit. However, compilation time (the time it takes to convert user design input into a functional implementation on the FPGA) has been a growing problem and is stifling designer productivity. This dissertation presents a new approach to FPGA compilation that more closely follows the software compilation model than that of the application specific integrated circuit (ASIC). Instead of re-compiling every module in the design for each invocation of the …

Improved Stereo Vision Methods For Fpga-Based Computing Platforms, Wade S. Fife

Theses and Dissertations

Stereo vision is a very useful, yet challenging technology for a wide variety of applications. One of the greatest challenges is meeting the computational demands of stereo vision applications that require real-time performance. The FPGA (Field Programmable Gate Array) is a readily-available technology that allows many stereo vision methods to be implemented while meeting the strict real-time performance requirements of some applications. Some of the best results have been obtained using non-parametric stereo correlation methods, such as the rank and census transform. Yet relatively little work has been done to study these methods or to propose new algorithms based on …

Fpga Bootstrapping Using Partial Reconfiguration, Patrick Sutton Ostler

Theses and Dissertations

Partial reconfiguration (PR) is the process of configuring a subset of resources on a Field Programmable Gate Array (FPGA) while the remainder of the device continues to operate. PR extends the usability of FPGAs and makes it possible to perform design bootstrapping. Just like bootstrapping in PCs, bootstrapping in FPGAs consists of using a small application to initialize basic services and load a larger, more complex application to the device. Bootstrapping allows for unique design applications that can be used to maintain communication services, increase design security, reduce initial configuration time, and reduce nonvolatile configuration memory storage. This thesis presents …

Development Of An Experimental Phased-Array Feed System And Algorithms For Radio Astronomy, Jonathan Charles Landon

Theses and Dissertations

Phased array feeds (PAFs) are a promising new technology for astronomical radio telescopes. While PAFs have been used in other fields, the demanding sensitivity and calibration requirements in astronomy present unique new challenges. This dissertation presents some of the first astronomical PAF results demonstrating the lowest noise temperature and highest sensitivity at the time (66 Kelvin and 3.3 m^2/K, respectively), obtained using a narrowband (425 kHz bandwidth) prototype array of 19 linear co-polarized L-band dipoles mounted at the focus of the Green Bank 20 Meter Telescope at the National Radio Astronomy Observatory (NRAO) in Green Bank, West Virginia. Results include …

Automated Fixed-Point Analysis And Bit Width Selection In Digital Signal Processing Circuits Using Ptolemy, Derrick S. Gibelyou

Theses and Dissertations

When designing custom hardware to implement signal processing algorithms, it is important to select bitwidths that meet the minimum error requirements while minimizing implementation area. Larger bitwidths reduce error, but increase area, while selecting smaller bitwidths does the opposite. Finding the set of bitwidths that produces the smallest area that still meets the error requirements has been shown to be NP-hard. To address this problem, many heuristics have been developed. Unfortunately, they are not always well documented and do not have available source code. It is also di cult to know which algorithm to try to use. This thesis addresses …

Fpga Communication Framework For Communication, Debugging, Testing, And Rapid Prototyping, Peter Andrew Lieber

Theses and Dissertations

FPGA-CF is an open-source, portable, extensible communications framework that consists of a small hardware core (less than 600 slices) and a software library/API (Java and C++). It enables a host PC to transmit data at 120 Mb/s to Xilinx-based FPGA boards via Ethernet using standard inter-networking protocols (UDP/IP). A custom lightweight connection-oriented protocol guarantees reliability. The hardware core is directly connected to the Xilinx internal configuration port (ICAP) and supports all ICAP functionality. The core also provides an extensible user-channel interface and provides up to 15, 8-bit user-data channels that can be connected to user circuitry (configurable by the user). …

Fm Demodulators In Software-Defined Radio Using Fpgas With Rapid Prototyping, Marc Anthony Padilla

Theses and Dissertations

With the advent of software-defined radio, many radio applications have and are currently being designed for FPGAs, due to their high performance and reconfigurability. Invariably, "legacy" waveforms, such as FM, will need to be supported in such systems. A challenge that comes with programming FPGAs is the increased design and implementation time over conventional software programming. In this thesis, three FM demodulator techniques are implemented and compared in an FPGA. Two techniques are found to have similar SNR performance while having very different FPGA implementation characteristics. Library based design is explored for demodulators to increase FPGA design productivity. A block …

Increasing Design Productivity For Fpgas Through Ip Reuse And Meta-Data Encapsulation, Adam T. Arnesen

Theses and Dissertations

As Moore's law continues to progress, it is becoming increasingly difficult for hardware designers to fully utilize the increasing number of transistors available semiconductor devices including FPGAs. This design productivity gap must be addressed to allow designs to take full advantage of the increased logic density that results from rising transistor density. The reuse of previously developed and verified intellectual property (IP) is one approach that has claimed to narrow the design productivity gap. Reuse, however, has proved difficult to realize in practice because of the complexity of IP and the reluctance of designers to reuse IP that they do …

Xdl-Based Hard Macro Generator, Subhrashankha Ghosh

Theses and Dissertations

In a conventional hardware design flow, the compilation process to create the physical circuit on the FPGA takes a long time. HMFlow is a design flow that reduces the compilation time by using pre-compiled modules called hard macros. HMFlow uses System Generator to create the designs, which are then converted to hard macros. The hard macro creation process takes a long time and a possible solution is a hard macro generator called XdlCoreGen, which is described in this thesis. XdlCoreGen can quickly create fully mapped and placed hard macros using XDL. XDL is a human readable design format that describes …

Analysis And Mitigation Of Seu-Induced Noise In Fpga-Based Dsp Systems, Brian Hogan Pratt

Theses and Dissertations

This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on digital signal processing (DSP) systems designed for field-programmable gate arrays (FPGAs). It presents a novel method for evaluating the effects of radiation on DSP and digital communication systems. By using an application-specific measurement of performance in the presence of SEUs, this dissertation demonstrates that only 5-15% of SEUs affecting a communications receiver (i.e. 5-15% of sensitive SEUs) cause critical performance loss. It also reports that the most critical SEUs are those that affect the clock, global reset, and most significant bits (MSBs) of computation. This dissertation also demonstrates …

On-Orbit Fpga Seu Mitigation And Measurement Experiments On The Cibola Flight Experiment Satellite, William A. Howes

Theses and Dissertations

This work presents on-orbit experiments conducted to validate SEU mitigation and detection techniques on FPGA devices and to measure SEU rates in FPGAs and SDRAM. These experiments were designed for the Cibola Flight Experiment Satellite (CFESat), which is an operational technology pathfinder satellite built around 9 Xilinx Virtex FPGAs and developed at Los Alamos National Laboratory. The on-orbit validation experiments described in this work have operated for over four thousand FPGA device days and have validated a variety of SEU mitigation and detection techniques including triple modular redundancy, duplication with compare, reduced precision redundancy, and SDRAM and FPGA block memory …

Global Positioning System, Vladimir Villalba

Electrical Engineering

The Global Positioning System (GPS) is a navigation network consisting of 24 satellites in orbit around the Earth. This satellite system provides the accurate position of an individual in all weather conditions at all times around the world. Individuals can use GPS receivers to locate where they are, pinpoint where they want to go with any form of transportation.

The senior project embarks in a path to understand the workings of the GPS satellite system. To accomplish this task, the concepts learned in Electrical Engineering will be implemented. This report encompasses the design process and steps taken in prototyping a …

Design Of An Adaptable Run-Time Reconfigurable Software-Defined Radio Processing Architecture, Joshua R. Templin

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

Processing power is a key technical challenge holding back the development of a high-performance software defined radio (SDR). Traditionally, SDR has utilized digital signal processors (DSPs), but increasingly complex algorithms, higher data rates, and multi-tasking needs have exceed the processing capabilities of modern DSPs. Reconfigurable computers, such as field-programmable gate arrays (FPGAs), are popular alternatives because of their performance gains over software for streaming data applications like SDR. However, FPGAs have not yet realized the ideal SDR because architectures have not fully utilized their partial reconfiguration (PR) capabilities to bring needed flexibility. A reconfigurable processor architecture is proposed that utilizes …

Analysis Of Field Programmable Gate Array-Based Kalman Filter Architectures, Arvind Sudarsanam

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

A Field Programmable Gate Array (FPGA)-based Polymorphic Faddeev Systolic Array (PolyFSA) architecture is proposed to accelerate an Extended Kalman Filter (EKF) algorithm. A system architecture comprising a software processor as the host processor, a hardware controller, a cache-based memory sub-system, and the proposed PolyFSA as co-processor, is presented. PolyFSA-based system architecture is implemented on a Xilinx Virtex 4 family of FPGAs. Results indicate significant speed-ups for the proposed architecture when compared against a space-based software processor. This dissertation proposes a comprehensive architecture analysis that is comprised of (i) error analysis, (ii) performance analysis, and (iii) area analysis. Results are presented …

A Bit Serial Approach To Massively Parallel Floating Point Operations On An Fpga, Duane Marcy, Fred Schlereth, Parija Kshirsagar, Anvith Katte Mahabalagiri

Electrical Engineering and Computer Science - All Scholarship

In this paper we discuss the pros and cons of bit serial arithmetic for performing mathematical operations for signal processing and scientific computations on an FPGA.  We describe our formulation of the architecture for such massively parallel systems, the advantage being that it requires no parallel programming in the traditional sense. We describe a pseudo floating point bit serial circuit which is less complex than full precision floating point and show that it is suitable for many applications. We conclude with several application examples and show that a bit serial implementation can be competitive with a high speed parallel implementation.

An Onboard Vision System For Unmanned Aerial Vehicle Guidance, Barrett Bruce Edwards

Theses and Dissertations

The viability of small Unmanned Aerial Vehicles (UAVs) as a stable platform for specific application use has been significantly advanced in recent years. Initial focus of lightweight UAV development was to create a craft capable of stable and controllable flight. This is largely a solved problem. Currently, the field has progressed to the point that unmanned aircraft can be carried in a backpack, launched by hand, weigh only a few pounds and be capable of navigating through unrestricted airspace. The most basic use of a UAV is to visually observe the environment and use that information to influence decision making. …

Case Study Of Finite Resource Optimization In Fpga Using Genetic Algorithm, Jingxia Wang, Sin Ming Loo

Electrical and Computer Engineering Faculty Publications and Presentations

Modem Field-Programmable Gate Arrays (FPGAs) are becoming very popular in embedded systems and high performance applications. FPGA has benefited from the shrinking of transistor feature size, which allows more on-chip reconfigurable (e.g., memories and look-up tables) and routing resources available. Unfortunately, the amount of reconfigurable resources in a FPGA is fixed and limited. This paper investigates the mapping scheme of the applications in a FPGA by utilizing sequential processing (e.g., Altera Nios II or Xilinx Microblaze, using C programming language) and task specific hardware (using hardware description language). Genetic Algorithm is used in this study. We found that placing sequential …

Optimizing Reconfigurable Hardware Resource Usage In System-On-A-Programmable-Chip With Location-Aware Genetic Algorithm, Sin Ming Loo, Jingxia Wang

Electrical and Computer Engineering Faculty Publications and Presentations

This paper presents static task scheduling using location-aware genetic algorithm techniques to schedule task systems to finite amounts of reconfigurable hardware. This research optimizes the use of limited reconfigurable resources. This scheduling algorithm is built upon our previous work [12- 14]. In this paper, the genetic algorithm has been expanded to include a feature to assign selected tasks to specific functional units. In this reconfigurable hardware environment, multiple sequential processing elements (soft core processors such as Xilinx MicroBlaze [22] or Altera Nios-II [1]), task-specific core (application specific hardware), and communication network within the reconfigurable hardware can be used (such a …

An Efficient Implementation Of An Exponential Random Number Generator In A Field Programmable Gate Array (Fpga), Smitha Gautham

Theses and Dissertations

Many physical, biological, ecological and behavioral events occur at times and rates that are exponentially distributed. Modeling these systems requires simulators that can accurately generate a large quantity of exponentially distributed random numbers, which is a computationally intensive task. To improve the performance of these simulators, one approach is to move portions of the computationally inefficient simulation tasks from software to custom hardware implemented in Field Programmable Gate Arrays (FPGAs). In this work, we study efficient FPGA implementations of exponentially distributed random number generators to improve simulator performance. Our approach is to generate uniformly distributed random numbers using standard techniques …

Synchronization Voter Insertion Algorithms For Fpga Designs Using Triple Modular Redundancy, Jonathan Mark Johnson

Theses and Dissertations

Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems that employ configuration scrubbing, majority voters are needed in all feedback paths to ensure proper synchronization between the TMR replicates. Synchronization voters, however, consume additional resources and impact system timing. This work introduces and contrasts seven algorithms for inserting synchronization voters while automatically performing TMR. The area cost and timing impact of each algorithm on a number of circuit benchmarks is reported. The work demonstrates that one of the algorithms provides the best overall timing …

New Approach Fpga-Based Implementation Of Discontinuous Svpwm}, Tole Sutikno, Auzani Jidin, Nik Rumzi Nik Idris

Turkish Journal of Electrical Engineering and Computer Sciences

The discontinuous space vector pulse-width modulation (DSVPWM) is a well-known technique offering lower switching losses than continuous SVPWM. At the same, average switching frequency, or a switching frequency 1.5 times higher than utilized in continuous SVPWM, the discontinuous SVPWM results in lower current harmonic distortions than that obtained in continuous SVPWM at high modulation indices. This paper is concerned with the design and realization of new FPGA approach based a 5-segment discontinuous SVPWM operated at 40 kHz switching frequency. It will be shown that the implementation of the discontinuous SVPWM utilized in FPGA, to execute some complex tasks, is simplified …

Reconfigurable Computing For Video Coding, Jian Huang

Electronic Theses and Dissertations

Video coding is widely used in our daily life. Due to its high computational complexity, hardware implementation is usually preferred. In this research, we investigate both ASIC hardware design approach and reconfigurable hardware design approach for video coding applications. First, we present a unified architecture that can perform Discrete Cosine Transform (DCT), Inverse Discrete Cosine Transform (IDCT), DCT domain motion estimation and compensation (DCT-ME/MC). Our proposed architecture is a Wavefront Array-based Processor with a highly modular structure consisting of 8*8 Processing Elements (PEs). By utilizing statistical properties and arithmetic operations, it can be used as a high performance hardware accelerator …

Efficient Implementation Of Raid-6 Encoding And Decoding On A Field Programmable Gate Array (Fpga), David Jacob

Theses and Dissertations

RAID-6 is a data encoding scheme used to provide single drive error detection and dual drive error correction for data redundancy on an array of disks. Here we present a thorough study of efficient implementations of RAID-6 on field programmable gate arrays (FPGAs). Since RAID-6 relies heavily on Galois Field Algebra (GFA), an efficient implementation of a GFA FPGA library is also presented. Through rigorous performance analysis, this work shows the most efficient ways to tradeoff FPGA resources and execution time when implementing GFA functions as well as RAID-6 encoding and decoding.

Bit Error Rate, Power And Area Analysis Of Multiple Fpga Implementations Of Underwater Fsk, Ying Li, Bridget Benson, Ryan Kastner, Xing Zhang

Electrical Engineering

There has been an increasing interest in creating short-range, low data-rate underwater wireless sensor networks for scientific marine exploration and monitoring. However, the lack of an inexpensive, low-power, underwater acoustic modem is preventing the proliferation of these sensor networks. Thus, we are building an underwater acoustic modem that considers cost and power at every level, from the analog electronics, to the modulation scheme, to the hardware platform. In this paper, we use reconfigurable devices to explore the design space of our modulation scheme – Frequency Shift Keying (FSK) – to select an implementation that provides the lowest power and area …

A Comprehensive Integration And Analysis Of Dynamic Load Balancing Architectures Within Molecular Dynamics, Christopher Reed Rogers

All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

The world of nano-science is an ever-changing field. Molecular Dynamics (MD) is a computational suite of tools that is useful for analyzing and predicting behaviors of substances on the molecular level. The nature of MD is such that only a few types of computations are repeated thousands or sometimes millions of times over. Even a small increase speedup or efficiency of an MD simulator can compound itself over the life of the simulation and have a positive and observable effect. This thesis is the end result of an attempted speedup of the MD problem. Two types of MD architectures are …

Real-Time Optical Flow Sensor Design And Its Application On Obstacle Detection, Zhaoyi Wei

Theses and Dissertations

Motion is one of the most important features describing an image sequence. Motion estimation has been widely applied in structure from motion, vision-based navigation and many other fields. However, real-time motion estimation remains a challenge because of its high computational expense. The traditional CPU-based scheme cannot satisfy the power, size and computation requirements in many applications. With the availability of new parallel architectures such as FPGAs and GPUs, applying these new technologies to computer vision tasks such as motion estimation has been an active research field in recent years. In this dissertation, FPGAs have been applied to real-time motion estimation …

An Optical Flow Implementation Comparison Study, John M. Bodily

Theses and Dissertations

Optical flow is the apparent motion of brightness patterns within an image scene. Algorithms used to calculate the optical flow for a sequence of images are useful in a variety of applications, including motion detection and obstacle avoidance. Typical optical flow algorithms are computationally intense and run slowly when implemented in software, which is problematic since many potential applications of the algorithm require real-time calculation in order to be useful. To increase performance of the calculation, optical flow has recently been implemented on FPGA and GPU platforms. These devices are able to process optical flow in real-time, but are generally …

Real-Time Carrier Frequency Estimation Using Disjoint Pilot Symbol Blocks, Joseph M. Palmer

Theses and Dissertations

Three new and efficient carrier frequency offset estimators are created for the case of disjoint pilot symbol blocks. The estimators are efficient in both a statistical sense and a computational sense. They are formulated to reduce computational cost for use in real-time applications, such as FPGA (field programmable gate array) devices. A reduced cost maximum likelihood (ML) frequency estimator is described. It is a generalization of the approximate ML estimator for a single block of pilot symbols. A number of recent ML estimation techniques are integrated with the purpose of reducing the computational cost while preserving estimation performance. The estimator …