Hardware Systems Commons^™

Nanomagnet Based Reservoir Computing And Quantum Control, Fahim F. Chowdhury

Theses and Dissertations

Conventional CMOS scaling has driven remarkable advances in computing but faces increasing physical and energy constraints, motivating alternative computing paradigms that integrate memory and computation while improving energy efficiency. Nanoscale magnetic systems offer a promising platform for such approaches because their intrinsic nonlinear dynamics and localized magnetic fields can support both classical and quantum information processing. This thesis investigates nanomagnetic systems for physical reservoir computing and, with primary emphasis, for localized quantum control of spin qubits.

The first part explores dipole-coupled nanomagnet arrays as physical reservoirs. Micromagnetic simulations demonstrate nonlinear dynamical behavior with high short-term memory and parity-check capacity, enabling …

Investigations Of Secure Memory For Vlsi Based Crypto System, Vijay Sai R Mr

Theses and Dissertations

Semiconductor technology is growing very rapidly in their architectural developments, involving the usage of processor and memory. Presence of memory, in general is a vital commodity in various devices which are almost embedded into human activity, from robust work stations to handy mobile phones. Security of data stored in memory is very important, and hence, observation must be made that these valuable data should not be thwarted by malicious means. Security in cache memory is a major issue in memory related applications such as smart cards and bio-metric implementations.

Cache, is a small and limited memory located between central processing …

Design And Implementation Of Uvm-Based Verification Framework For Deep Learning Accelerators, Randa Ahmed Hussein Aboudeif

Theses and Dissertations

Recent advancements in deep learning (DL) have made hardware accelerators, known as deep learning accelerators (DLAs), a preferred solution for numerous high-performance computing (HPC) applications, including speech recognition, computer vision, and image classification. DLAs are composed of hundreds of parallel processing engines to speed up computations and can gain access to pre-trained networks from the cloud or through on-chip memory to implement the DNN inference process. DLA verification is becoming an important and challenging phase. The verification process is required to handle the complex DLA design. Moreover, the reliability of DLAs is critical for assessment as they are involved in …

Investigating Hardware-Based Aes Countermeasures In The Sam4l Microcontroller For Side-Channel Attack Mitigation, Turki Mesbel Alamri

Theses and Dissertations

Side-channel attacks (SCAs) represent a sophisticated method by which attackers exploit indirect pathways, such as power leakage and electromagnetic emissions to glean sensitive information from microprocessors. These attacks analyze variation in power consumption during operations like data encryption to infer protected data, potentially compromising the security of the device. For example, observing the power draw differences when a device encrypts known data can also serve defensive purposes. Attacks often overlook emissions and power patterns, while focusing on avoiding network and host-based detection systems. This oversight presents an opportunity for security professionals to use SCAs to enhance system defenses by monitoring …

Adaptive Traction, Power And Torque Control Strategies And Optimization In An All-Electric Powertrain, Aymane Hidara

Theses and Dissertations

Electric and hybrid-electric vehicles lean heavily on intricate control algorithms to provide smooth, reliable, and secure operations under any driving conditions. Three distinct supervisory control strategies have been developed, each aiming to improve reliability and vehicle performance of a dual-motor electric vehicle equipped with an all-wheel-drive, fully electric powertrain. These algorithms are adept at dynamically modulating and constraining the torque provided to the wheels, leveraging two autonomous permanent magnet electric drive units. This study utilizes a vehicle model jointly provided by MathWorks and General Motors in partnership with industry sponsors. The these strategies were implemented in the model and enhanced …

Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya

Theses and Dissertations

High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a …

Wifi Sensing At The Edge Towards Scalable On-Device Wireless Sensing Systems, Steven M. Hernandez

Theses and Dissertations

WiFi sensing offers a powerful method for tracking physical activities using the radio-frequency signals already found throughout our homes and offices. This novel sensing modality offers continuous and non-intrusive activity tracking since sensing can be performed (i) without requiring wearable sensors, (ii) outside the line-of-sight, and even (iii) through the wall. Furthermore, WiFi has become a ubiquitous technology in our computers, our smartphones, and even in low-cost Internet of Things devices. In this work, we consider how the ubiquity of these low-cost WiFi devices offer an unparalleled opportunity for improving the scalability of wireless sensing systems. Thus far, WiFi sensing …

Design, Development And Evaluation Of The Ruggedized Edge Computing Node (Recon), Sahil Girin Patel

Theses and Dissertations

The increased quality and quantity of sensors provide an ever-increasing capability to collect large quantities of high-quality data in the field. Research devoted to translating that data is progressing rapidly; however, translating field data into usable information can require high performance computing capabilities. While high performance computing (HPC) resources are available in centralized facilities, bandwidth, latency, security and other limitations inherent to edge location in field sensor applications may prevent HPC resources from being used in a timely fashion necessary for potential United States Army Corps of Engineers (USACE) field applications. To address these limitations, the design requirements for RECON …

Securing Infiniband Networks With End-Point Encryption, Noah B. Diamond

Theses and Dissertations

The NVIDIA-Mellanox Bluefield-2 is a 100 Gbps high-performance network interface which offers hardware offload and acceleration features that can operate directly on network traffic without routine involvement from the ARM CPU. This allows the ARM multi-core CPU to orchestrate the hardware to perform operations on both Ethernet and RDMA traffic at high rates rather than processing all the traffic directly. A testbed called TNAP was created for performance testing and a MiTM verification process called MiTMVMP is used to ensure proper network configuration. The hardware accelerators of the Bluefield-2 support a throughput of nearly 86 Gbps when using IPsec to …

Evaluating The Use Of Boot Image Encryption On Talos Ii Architecture, Calvin M. Muramoto

Theses and Dissertations

Sensitive devices operating in unprotected environments are vulnerable to hardware attacks like reverse engineering and side channel analysis. This represents a security concern because the root of trust can be invalidated through boot firmware manipulation. For example, boot data is rarely encrypted and typically travels across an accessible bus like the LPC bus, allowing data to be easily intercepted and possibly manipulated during system startup. The ash chip storing the boot data can also be removed from these devices and examined to reveal detailed boot information. This paper details an implementation of encrypting a section of the boot image and …

Implementation And Characterization Of Ahr On A Xilinx Fpga, Andrew J. Dittrich

Theses and Dissertations

A new version of the Adaptive-Hybrid Redundancy (AHR) architecture was developed to be implemented and tested in hardware using Commercial-Off-The-Shelf (COTS) Field-Programmable Gate Arrays (FPGAs). The AHR architecture was developed to mitigate the effects that the Single Event Upset (SEU) and Single Event Transient (SET) radiation effects have on processors and was tested on a Microprocessor without Interlocked Pipeline Stages (MIPS) architecture. The AHR MIPS architecture was implemented in hardware using two Xilinx FPGAs. A Universal Asynchronous Receiver Transmitter (UART) based serial communication network was added to the AHR MIPS design to enable inter-board communication between the two FPGAs. The …

Design, Development, And Testing Of Embedded Computing On Afit's Control & Autonomy Space Proximity Robot (Caspr), Collin A. Gwaltney

Theses and Dissertations

This thesis reviews RPO algorithm testbeds and discusses the development of the Control and Autonomy Space proximity Robot (CASpR) kinematic testbed housed at the Air Force Institute of Technology (AFIT). CASpR operates on a rail system to propagate the trajectories of two satellites using the Hill-Clohessy-Wiltshire (HCW) Equations of Motion (EOMs). In this study, the implementation of a Jetson TX2i as an onboard flight computer is discussed and accomplished. Each hardware component used in the process of adding embedded computing as well as the software and paths of communication are all discussed in detail. Tests are conducted to assess the …

Physically Unclonable Characteristics For Verification Of Transmon-Based Quantum Computers, Leleia A. Hsia

Theses and Dissertations

Future national security can be strengthened by verifying and securing the quantum computing supply chain. This dissertation proposes physically unclonable characteristics (PUCs), a method of quantum hardware verification inspired by classical physically unclonable functions, for future application to quantum processors implemented with transmon qubits. Qualitative and quantitative analysis is provided on the development of PUCs, including identifying qubit characteristics and qubit discrimination methods suitable for PUCs. Characteristics tested on IBM Quantum services include T1 and T2 coherence times, single-qubit and multi-qubit gate error rates, readout error rates, quantum process tomography metrics, and random benchmarking metrics. Results show that non-parametric qubit …

A General Framework For Characterizing And Evaluating Attacker Models For Cps Security Assessment, Christopher S. Deloglos, Christopher Deloglos

Theses and Dissertations

Characterizing the attacker’s perspective is essential to assessing the security posture and resilience of cyber-physical systems. The attacker’s perspective is most often achieved by cyber-security experts (e.g., red teams) who critically challenge and analyze the system from an adversarial stance. Unfortunately, the knowledge and experience of cyber-security experts can be inconsistent leading to situations where there are gaps in the security assessment of a given system. Structured security review processes (such as TAM, Mission Aware, STPA-SEC, and STPA-SafeSec) attempt to standardize the review processes to impart consistency across an organization or application domain. However, with most security review processes, the …

Novel On-Chip Optical Modulator Designs, Mohamed Mahmoud Ibrahim Ibrahim Elsayed

Theses and Dissertations

The huge increments in data traffic and communication over the past few decades have pushed the conventional electronic communication systems to their physical limits in terms of data rate, bandwidth and capacity. The continuous shrinking of feature sizes, the increase in the microelectronic integrated circuits complexity, and the increasing demand for higher speeds and data rates have all stimulated seeking new technology to replace the currently present microelectronics industry rather than improving it. Photonics is one of the most likely candidates to answer this pursuit for its compatibility with the fiber optic industry, which has shown a great success in …

Implementation Of A Hierarchical, Embedded, Cyber Attack Detection System For Spi Devices On Unmanned Aerial Systems, Jeremy J. Price

Theses and Dissertations

Unmanned Aerial Systems (UAS) create security concerns as their roles expand in commercial, military, and consumer spaces. The need to secure these systems is recognized in the architecture for a Hierarchical, Embedded, Cyber Attack Detection (HECAD) system. HECAD passively monitors the communication between a flight controller and all its peripherals like sensors and actuators. It ensures the functionality of a UAS is within the set of defined behavior and reports all potential problems, whether the errors were caused by cyber attacks or other physical faults. A portion of the design for Serial Peripheral Interface (SPI) devices on board a flight …

Adaptive-Hybrid Redundancy For Radiation Hardening, Nicolas S. Hamilton

Theses and Dissertations

An Adaptive-Hybrid Redundancy (AHR) mitigation strategy is proposed to mitigate the effects of Single Event Upset (SEU) and Single Event Transient (SET) radiation effects. AHR is adaptive because it switches between Triple Modular Redundancy (TMR) and Temporal Software Redundancy (TSR). AHR is hybrid because it uses hardware and software redundancy. AHR is demonstrated to run faster than TSR and use less energy than TMR. Furthermore, AHR allows space vehicle designers, mission planners, and operators the flexibility to determine how much time is spent in TMR and TSR. TMR mode provides faster processing at the expense of greater energy usage. TSR …

Graph-Based Temporal Analysis In Digital Forensics, Nikolai A. Adderley

Theses and Dissertations

Establishing a timeline as part of a digital forensics investigation is a vital part of understanding the order in which system events occurred. However, most digital forensics tools present timelines as histogram or as raw artifacts. Consequently, digital forensics examiners are forced to rely on manual, labor-intensive practices to reconstruct system events. Current digital forensics analysis tools are at their technological limit with the increasing storage and complexity of data. A graph-based timeline can present digital forensics evidence in a structure that can be immediately understood and effortlessly focused. This paper presents the Temporal Analysis Integration Management Application (TAIMA) to …

Instantaneous Bandwidth Expansion Using Software Defined Radios, Nicholas D. Everett

Theses and Dissertations

The Stimulated Unintended Radiated Emissions (SURE) process has been proven capable of classifying a device (e.g. a loaded antenna) as either operational or defective. Currently, the SURE process utilizes a specialized noise radar which is bulky, expensive and not easily supported. With current technology advancements, Software Defined Radios (SDRs) have become more compact, more readily available and significantly cheaper. The research here examines whether multiple SDRs can be integrated to replace the current specialized ultra-wideband noise radar used with the SURE process. The research specifically targets whether or not multiple SDR sub-band collections can be combined to form a wider …

Toward Biologically-Inspired Self-Healing, Resilient Architectures For Digital Instrumentation And Control Systems And Embedded Devices, Shawkat Sabah Khairullah

Theses and Dissertations

Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes. One of the more essential concepts for achieving this goal is the notion of resilient and survivable digital I&C systems. In recent years, self-healing concepts based on biological physiology have received attention for the design of robust digital systems. However, many of these approaches have not been architected from the outset with safety in mind, nor have they been targeted for the automation community where a significant need exists. This dissertation presents a new self-healing digital …

A Framework For Understanding, Prioritizing, And Applying Systems Security Engineering Processes, Activities, And Tasks, Stephen Khou

Theses and Dissertations

Current systems security practices lack an effective approach to prioritize and tailor systems security efforts to develop and field secure systems in challenging operational environments, which results in business and mission stakeholders becoming more susceptible to an array of disruptive events. This work informs Systems Engineers on recent developments in the field of system security engineering and provides a framework for more fully understanding the application of Systems Security Engineering (SSE) processes, activities, and tasks as described in the recently released National Institute of Standards and Technology (NIST) Special Publication 800-160. This SSE framework uniquely offers a repeatable and tailorable …

An Analysis Of Conus Based Deployment Of Pseudolites For Positioning, Navigation And Timing (Pnt) Systems, Justin H. Deifel, Albert J. Pena

Theses and Dissertations

The Global Positioning System (GPS) developed and operated by the United States Air Force (USAF) provides a way for users to determine position, navigation and timing (PNT). GPS provides an extraordinary capability that has become instrumental in all aspects of our day to day lives. As new technologies such as automated vehicles and unmanned aircraft continue to be developed, a reliable back up to GPS is required to ensure the PNT data generated in these systems is accurate. This research studies a potential architecture for deploying a nationwide network of ground based pseudolites that would act to supplement and backup …

Design Of An All-In-One Embedded Flight Control System, Joel D. Elmore

Theses and Dissertations

This thesis describes an all-in-one flight control system (FCS) that was designed for unmanned aerial vehicles (UAVs). The project focuses on the embedded hardware aspect of a stand-alone system with low-cost and reliability in mind.

Radio Frequency Based Programmable Logic Controller Anomaly Detection, Samuel J. Stone

Theses and Dissertations

The research goal involved developing improved methods for securing Programmable Logic Controller (PLC) devices against unauthorized entry and mitigating the risk of Supervisory Control and Data Acquisition (SCADA) attack by detecting malicious software and/or trojan hardware. A Correlation Based Anomaly Detection (CBAD) process was developed to enable 1) software anomaly detection discriminating between various operating conditions to detect malfunctioning or malicious software, firmware, etc., and 2) hardware component discrimination discriminating between various hardware components to detect malfunctioning or counterfeit, trojan, etc., components.

File Carving And Malware Identification Algorithms Applied To Firmware Reverse Engineering, Karl A . Sickendick

Theses and Dissertations

Modern society depends on critical infrastructure (CI) managed by Programmable Logic Controllers (PLCs). PLCs depend on firmware, though firmware security vulnerabilities and contents remain largely unexplored. Attackers are acquiring the knowledge required to construct and install malicious firmware on CI. To the defender, firmware reverse engineering is a critical, but tedious, process. This thesis applies machine learning algorithms, from the le carving and malware identification fields, to firmware reverse engineering. It characterizes the algorithms' performance. This research describes and characterizes a process to speed and simplify PLC firmware analysis. The system partitions binary firmwares into segments, labels each segment with …

External Verification Of Scada System Embedded Controller Firmware, Lucille R. Mcminn

Theses and Dissertations

Critical infrastructures such as oil and gas pipelines, the electric power grid, and railways, rely on the proper operation of supervisory control and data acquisition (SCADA) systems. Current SCADA systems, however, do not have sufficient tailored electronic security solutions. Solutions available are developed primarily for information technology (IT) systems. Indeed, the toolkit for SCADA incident prevention and response is unavailing as the operating parameters associated with SCADA systems are different from IT systems. The unique environment necessitates tailored solutions. Consider the programmable logic controllers (PLCs) that directly connect to end physical systems for control and monitoring of operating parameters -- …

Dynamic Polymorphic Reconfiguration To Effectively “Cloak” A Circuit’S Function, Jeffrey L. Falkinburg

Theses and Dissertations

Today's society has become more dependent on the integrity and protection of digital information used in daily transactions resulting in an ever increasing need for information security. Additionally, the need for faster and more secure cryptographic algorithms to provide this information security has become paramount. Hardware implementations of cryptographic algorithms provide the necessary increase in throughput, but at a cost of leaking critical information. Side Channel Analysis (SCA) attacks allow an attacker to exploit the regular and predictable power signatures leaked by cryptographic functions used in algorithms such as RSA. In this research the focus on a means to counteract …

Automated Analysis Of Arm Binaries Using The Low-Level Virtual Machine Compiler Framework, Jeffrey B. Scott

Theses and Dissertations

Binary program analysis is a critical capability for offensive and defensive operations in Cyberspace. However, many current techniques are ineffective or time-consuming and few tools can analyze code compiled for embedded processors such as those used in network interface cards, control systems and mobile phones. This research designs and implements a binary analysis system, called the Architecture-independent Binary Abstracting Code Analysis System (ABACAS), which reverses the normal program compilation process, lifting binary machine code to the Low-Level Virtual Machine (LLVM) compiler's intermediate representation, thereby enabling existing security-related analyses to be applied to binary programs. The prototype targets ARM binaries but …

Image Processing For Multiple-Target Tracking On A Graphics Processing Unit, Michael A. Tanner

Theses and Dissertations

Multiple-target tracking (MTT) systems have been implemented on many different platforms, however these solutions are often expensive and have long development times. Such MTT implementations require custom hardware, yet offer very little flexibility with ever changing data sets and target tracking requirements. This research explores how to supplement and enhance MTT performance with an existing graphics processing unit (GPU) on a general computing platform. Typical computers are already equipped with powerful GPUs to support various games and multimedia applications. However, such GPUs are not currently being used in desktop MTT applications. This research explores if and how a GPU can …

Optimal Guidance Of A Relay Mav For Isr Support Beyond Line-Of-Sight, John H. Hansen

Theses and Dissertations

This thesis developed guidance laws to optimally position a relay Micro-UAV (MAV) to provide an operator with real-time Intelligence, Surveillance, and Reconnaissance (ISR) by relaying communication and video signals when there is no line-of-sight between the operator at the base and the rover MAV performing the ISR mission. The ISR system consists of two MAVs, the Relay and the Rover, and a Base. The Relay strives to position itself to minimize the radio frequency (RF) power required for maintaining communications between the Rover and the Base, while the Rover performs the ISR mission, which may maximize the required RF power. …