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Articles 31 - 46 of 46
Full-Text Articles in Hardware Systems
Hardware Algorithm Implementation For Mission Specific Processing, Jason W. Shirley
Hardware Algorithm Implementation For Mission Specific Processing, Jason W. Shirley
Theses and Dissertations
There is a need to expedite the process of designing military hardware to stay ahead of the adversary. The core of this project was to build reusable, synthesizeable libraries to make this a possibility. In order to build these libraries, Matlab® commands and functions, such as Conv2, Round, Floor, Pinv, etc., had to be converted into reusable VHDL modules. These modules make up reusable libraries for the Mission Specific Process (MSP) which will support AFRL/RY. The MSP allows the VLSI design process to be completed in a mere matter of days or months using an FPGA or ASIC design, as …
Radar System Characterization Extended To Hardware In The Loop Simulation For The Lab-Volt™ Training System, Oscar C. Mayhew
Radar System Characterization Extended To Hardware In The Loop Simulation For The Lab-Volt™ Training System, Oscar C. Mayhew
Theses and Dissertations
Modeling RADAR signals in software allows the testing of potential electronic counter measures and electronic counter counter measures without the associated RADAR hardware and test facilities. Performing a characterization process on a real world RADAR system reveals all imperfections within the system. The Lab-Volt™ RADAR system served as the characterized real world RADAR system. The characterization process consisted of measurements at selected front panel locations on the Lab-Volt™ transmitter module, antenna pedestal, receiver module, and dual channel sampler module. Due to the overwhelming influence of antenna parameters on a received signal, the characterization process also attempted to derive an antenna …
Real-Time Gps-Alternative Navigation Using Commodity Hardware, Jordon L. Fletcher
Real-Time Gps-Alternative Navigation Using Commodity Hardware, Jordon L. Fletcher
Theses and Dissertations
Modern navigation systems can use the Global Positioning System (GPS) to accurately determine position with precision in some cases bordering on millimeters. Unfortunately, GPS technology is susceptible to jamming, interception, and unavailability indoors or underground. There are several navigation techniques that can be used to navigate during times of GPS unavailability, but there are very few that result in GPS-level precision. One method of achieving high precision navigation without GPS is to fuse data obtained from multiple sensors. This thesis explores the fusion of imaging and inertial sensors and implements them in a real-time system that mimics human navigation. In …
Aphid: Anomaly Processor In Hardware For Intrusion Detection, Samuel A. Hart
Aphid: Anomaly Processor In Hardware For Intrusion Detection, Samuel A. Hart
Theses and Dissertations
The Anomaly Processor in Hardware for Intrusion Detection (APHID) is a step forward in the field of co-processing intrusion detection mechanism. By using small, fast hardware primitives APHID relieves the production CPU from the burden of security processing. These primitives are tightly coupled to the CPU giving them access to critical state information such as the current instruction(s) in execution, the next instruction, registers, and processor state information. By monitoring these hardware elements, APHID is able to determine when an anomalous action occurs within one clock cycle. Upon detection, APHID can force the processor into a corrective state, or a …
Hardware Virtualization Applied To Rootkit Defense, Douglas P. Medley
Hardware Virtualization Applied To Rootkit Defense, Douglas P. Medley
Theses and Dissertations
This research effort examines the idea of applying virtualization hardware to enhance operating system security against rootkits. Rootkits are sets of tools used to hide code and/or functionality from the user and operating system. Rootkits can accomplish this feat through using access to one part of an operating system to change another part that resides at the same privilege level. Hardware assisted virtualization (HAV) provides an opportunity to defeat this tactic through the introduction of a new operating mode. Created to aid operating system virtualization, HAV provides hardware support for managing and saving multiple states of the processor. This hardware …
Hardware Realization Of A Transform Domain Communication System, Marshall E. Haker
Hardware Realization Of A Transform Domain Communication System, Marshall E. Haker
Theses and Dissertations
The purpose of this research was to implement a Transform Domain Communication System (TDCS) in hardware and compare experimental bit error performance with results published in literature. The intent is to demonstrate the effectiveness or ineffectiveness of a TDCS in communicating binary data across a real channel. In this case, an acoustic channel that is laden with narrowband interference was considered. A TDCS user pair was constructed to validate the proposed design using Matlab™ to control a PC sound card. The proposed TDCS design used the Bartlett method of spectrum estimation, the spectral notching algorithm found in TDCS literature, quadrature …
Congruent Weak Conformance, Ronald W. Brower
Congruent Weak Conformance, Ronald W. Brower
Theses and Dissertations
This research addresses the problem of verifying implementations against specifications through an innovative logic approach. Congruent weak conformance, a formal relationship between agents and specifications, has been developed and proven to be a congruent partial order. This property arises from a set of relations called weak conformations. The largest, called weak conformance, is analogous to Milner's observational equivalence. Weak conformance is not an equivalence, however, but rather an ordering relation among processes. Weak conformance allows behaviors in the implementation that are unreachable in the specification. Furthermore, it exploits output concurrencies and allows interleaving of extraneous output actions in the implementation. …
Rapid And Accurate Timing Simulation Of Radiation-Hardened Digital Microelectronics Using Vhdl, Charles P. Brothers Jr.
Rapid And Accurate Timing Simulation Of Radiation-Hardened Digital Microelectronics Using Vhdl, Charles P. Brothers Jr.
Theses and Dissertations
This dissertation presents the development of a fast, accurate, timing simulation capability based on VHSIC Hardware Description Language VHDL without the use of back annotation of timing delay information. This VHDL-based timing simulator is intended for use with radiation-hardened microelectronics in simulating timing of circuit operation in pre-radiation, post-radiation 1 MradSi total dose, and ionizing dose radiation environments. Development of the timing models are presented. The implementation of the timing models are incorporated into a VHDL library composed of basic logic gates and flip-flops. Simulations of complex circuits were run in SPICE and VHDL to assess the timing accuracy and …
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Theses and Dissertations
Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural …
Virtual Memory Management And Virtual Bus Overloading On Multiple Channel Architectures, John N. Armitstead
Virtual Memory Management And Virtual Bus Overloading On Multiple Channel Architectures, John N. Armitstead
Theses and Dissertations
Today's computational environment requires the processing capabilities available only through parallel architectures. The bottleneck that limits the potential of parallel processing is communication between processors, memories, and other hardware devices. A proposed multiple channel architecture (MCA) utilizes tunable semiconductor lasers and fiber optic cables that serve as the communication medium between processor, memory, and I/O nodes. A memory management unit (MMU) was completely described and implemented in a multiprocessor simulator. A permutation-based interleaving (PBI) scheme was utilized to reduce the chance of memory access collisions. Virtual bus utilization, number of collisions, and message traffic patterns were studied under various amounts …
Design Of A Parallel Discrete Event Simulation Coprocessor, Jacob L. Berlin
Design Of A Parallel Discrete Event Simulation Coprocessor, Jacob L. Berlin
Theses and Dissertations
A Parallel Discrete Event Simulation Coprocessor was designed to off- load the synchronization overhead from the processors executing the application. In a multiprocessor architecture, one coprocessor executes the synchronization routines for each host processor. Speedup can be achieved when the host processor executes the application and the coprocessor concurrently executes synchronization routines. The coprocessor uses a programmable microcode control store to guarantee flexibility in the synchronization routines. The coprocessor uses an Extreme Search Associative Memory to support fast Next Event Queue NEQ management. This associative memory uses bit-serial word-parallel search logic to provide 01 insert and retrieval time of events …
A Decision Criteria To Select An Associative-Memory Organization That Minimizes The Execution Time Of A Mix Of Associative-Search Operations, David W. Banton
A Decision Criteria To Select An Associative-Memory Organization That Minimizes The Execution Time Of A Mix Of Associative-Search Operations, David W. Banton
Theses and Dissertations
The dissertation develops a decision criteria to select an associative-memory organization that minimizes the execution time of a mix of associative-search operations and a decision criteria to estimate the layout dimensions of each organization for a specified memory size. The dissertation reclassifies Feng's associative-search operations into three hardware-influenced categories: bit-position independent (BPI), record-content independent (RCI); bit-position dependent (BPD), RCI; and BPD, record-content dependent (RCD). It develops a relationship between the categories and three associative-memory organizations: the CAM, the bit-serial word-parallel associative memory (BSWPAM) , and the extreme-search associative memory (ESAM). A version of the CAM, three versions of the BSWPAM, …
Design Of A Hardware Discrete Event Simulation Coprocessor, David W. Daniel
Design Of A Hardware Discrete Event Simulation Coprocessor, David W. Daniel
Theses and Dissertations
A hardware discrete event simulation (DES) coprocessor was designed to eliminate synchronization overhead as a possible bottleneck. The target architecture is an eight node Intel iPSC/2 Hypercube, but this design has application to future CPU designs that wish to incorporate on-chip architectural features to better support parallel processor synchronization. A structural description of a general-purpose DES hardware coprocessor is given with approximately 90 percent of the components written at the gate level. The remaining components use low-level behavioral descriptions. While the DES coprocessor microcode implements the Chandy-Misra protocol, general-purpose support for a wide-range of protocols was a primary hardware design …
Formalizing, Validating, And Verifying Real-Time System Requirements With Reacto And Vhdl, Frank C. Young
Formalizing, Validating, And Verifying Real-Time System Requirements With Reacto And Vhdl, Frank C. Young
Theses and Dissertations
We develop a methodology for formalizing, verifying, and validating the requirements specification of real-time systems based on a graphical and formal hierarchical Finite State Machine (FSM) language Reacto. We define a means to quantify time and express real-time constraints in Reacto and a transformation from Reacto to the Very High Speed Integrated Circuit (VHSIC) hardware Description Language (VHDL). Reacto's high level abstractions, graphical nature, and theorem prover produce efficient, accurate, and easily understood specifications. We use VHDL's event driven simulation capability, concurrency, and temporal operators to thoroughly examine temporal dependencies between the state machine transitions, and to increase simulation power …
A Vhdl Interpreter For Model-Based Diagnoses, David R. Griffin
A Vhdl Interpreter For Model-Based Diagnoses, David R. Griffin
Theses and Dissertations
Model-based reasoning permits diagnostic applications to be written without waiting for someone to become an 'expert' of the system. For model-based diagnostics, there must be a model to reason from. This thesis explores using a VHDL description of the system as that model. A system based around a VHDL interpreter was written specifically for a model-based diagnostic algorithm. Currently, the diagnostic system uses an algorithm by Dries. This algorithm was derived from Scarl's Full Consistency Algorithm. The system was designed to be modular so that different diagnostic techniques could be implemented. It is divided into three parts: a VHDL parser, …
Requirements Analysis For A Hardware, Discrete-Event, Simulation Engine Accelerator, Paul J. Taylor Jr.
Requirements Analysis For A Hardware, Discrete-Event, Simulation Engine Accelerator, Paul J. Taylor Jr.
Theses and Dissertations
An analysis of a general Discrete Event Simulation (DES), executing on the distributed architecture of an eight mode Intel PSC/2 hypercube, was performed. The most time consuming portions of the general DES algorithm were determined to be the functions associated with message passing of required simulation data between processing nodes of the hypercube architecture. A behavioral description, using the IEEE standard VHSIC Hardware Description and Design Language (VHDL), for a general DES hardware accelerator is presented. The behavioral description specifies the operational requirements for a DES coprocessor to augment the hypercube's execution of DES simulations. The DES coprocessor design implements …