Digital Circuits Commons^™

Asynchronous Mips Processors: Educational Simulations, Robert L. Webb

Master's Theses

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …

5 Ghz Band Vehicle-To-Vehicle Channels: Models For Multiple Values Of Channel Bandwidth, Qiong Wu, David W. Matolak, Indranil Sen

Faculty Publications

In Sen and Matolak's earlier paper, 5-GHz-band vehicle-to-vehicle (V2V) channel models were presented for channel bandwidths of 5 and 10 MHz. In this paper, we provide additional tapped delay line models for bandwidths of 1, 20, 33.33, and 50 MHz based upon the data used in Sen and Matolak's paper. We provide tables of channel parameters for five types of V2V channel classes and also include example tap correlation coefficients. Root-mean-square delay spread values are summarized, as are values of bandwidth for which the channel frequency correlation takes values of 0.7 and 0.5. As with the results from Sen and …

High Power Microwave (Hpm) And Ionizing Radiation Effects On Cmos Devices, Nicholas A. Estep

Theses and Dissertations

Integrated circuits (ICs) are inherently complicated and made worse by increasing transistor quantity and density. This trend potentially enhances concomitant effects of high energy radiation and local or impressed electromagnetic interference (EMI). The reduced margin for signal error may counter any gain in radiation hardness from smaller device dimensions. Isolated EMI and ionizing radiation studies on circuits have been conducted extensively over the past 30 years. However, little focus has been placed on the combined effects. To investigate the effect of combined EMI and ionizing radiation, two complementary metal oxide semiconductor (CMOS) inverter technologies (CD4069 and SN74AUC1G04) were analyzed for …

Unidirectional Cordic For Efficient Computation Of Trigonometric And Hyperbolic Functions, Satish Ravichandran

Electrical & Computer Engineering Theses & Dissertations

CORDIC (Coordinate Rotation Digital Computer) is an iterative algorithm to compute values of trigonometric, logarithmic and transcendental functions by performing vector rotations, which can be implemented with only shift and add operations in a digital system. CORDIC algorithms are extensively used in the areas of digital signal processing, digital image processing and artificial neural networks. A new technique, named unidirectional CORDIC, for efficient computation of trigonometric and hyperbolic functions is presented in this thesis. In the conventional CORDIC algorithm, the vector rotations are performed in both clockwise and counterclockwise directions, but in the unidirectional CORDIC the vectors are rotated only …

Analysis Of Error Recovery Effects On Digital Flight Control Systems, Arturo Tejada Ruiz

Electrical & Computer Engineering Theses & Dissertations

Life-critical, real-time applications like flight-by-wire aircraft, rely on closed-loop digital control systems and fault-tolerant computer systems to reliably achieve the desired operation. The computer systems, however, may be affected by random hardware/software faults induced mainly by environmental conditions such as high intensity radiated fields (HIRF) and lightning. These harsh electromagnetic environments are known to induce common­ mode faults (CMF) in aircraft electronic systems, which disrupt fault-tolerant provisions and possibly affect the operation of the digital control system. Current flight-by-wire aircraft have computer systems that can neither detect CMF nor recover from them. New systems are under investigation that can recover …

Implementation Of Large Neural Networks Using Decomposition, Henry Selvaraj, H. Niewiadomski, P. Buciak, M. Pleban, Piotr Sapiecha, Tadeusz Luba, Venkatesan Muthukumar

Electrical & Computer Engineering Faculty Research

The article presents methods of dealing with huge data in the domain of neural networks. The decomposition of neural networks is introduced and its efficiency is proved by the authors’ experiments. The examinations of the effectiveness of argument reduction in the above filed, are presented. Authors indicate, that decomposition is capable of reducing the size and the complexity of the learned data, and thus it makes the learning process faster or, while dealing with large data, possible. According to the authors experiments, in some cases, argument reduction, makes the learning process harder.

A Vhdl Implementation Of Bist Technique In Uart Design, Mohd. Yamani Idna Idris

Student Works (2000-2009)

No abstract provided.

Rekabentuk Perkakasan Khas Ecc (Reed-Solomon), Muhamad Mursid Noorizan

Student Works (2000-2009)

Dokumen ini disiapknn bagi menyediakan laporan tentang perjalanan projek perkakasan khas ECC yang dijalankan. Bahagian pertama dokumen ini terdapat pengenalan tentang projek. Bahagian kedua pula menyatakan tentang kajian yang telah dilakukan bagi memilih kod-kod pembetulan yang ingin dibangunkan. Seterusnya pada bahagian tiga, dinyatakan serba sedikit tentang bahasa yang digunakan dalam pembangunan projek iaitu VHDL. Sahagian keempat pula menceritakan tentang senibina-senibina dan rekabentuk-rekabentuk perkakasan khas. Dalam bahagian lima, dokumen menceritakan tentang fasa pembangunan yang telah dijalankan. Bahagian enam dan tujuh pula menceritakan tentang perbincangan dan kesimpulan daripada projek yang telah dijalankan.

Pendarab Titik Apungan 32bit Bertalian Paip, Noorzaily Mohamed Noor

Student Works (2000-2009)

Tesis ini menghuraikan sebuah pendarab titik apungan 32bit bertalian paip 18MHz yang direkabentuk menggunakan bahasa perihalan perkakasan YHDL, peralatan sintesis Synopsys FPGA Express dan ·peralatan pemetaan Xilinx Alliance, PTA ini menggunakan 1007 CLB dan 100 10B di mana peranti pemetaan yang digunakan ialah xc4036xl-bg432-2 daripada pustaka XC4000 Xilinx FPGA. Pendarab ini mengandungi tiga tahap talian paip yang belainan fungsi. Tahap pertama melaksanakan penjanaan dedarab dan penambahan dedarab secara carry save dan penambahan eksponen. la menggunakan algoritma Booth tertib kedua dan pepohon Wallace dengan pemampat 4-2. Tahap kcdua pula melakukan penambahan bawaan rambatan akhir, penormalan mantisa dan pembetulan eksponen manakala tahap …

Mekanisma Pengujian Alu Menggunakan Teknik Boundary Scan, Abdul Aziz Ahmad Zaki Zamani

Student Works (2000-2009)

ALU testing mechanism using Boundary Scan technique is a project which is develop to be the tester for testing the digital circuit, integrated circuit and computer chip. The goal of this project is to develop a mechanism and as well building an ALU chip so that we will able to test and determine whether the chips are in a good shape and condition. This project contains two parts: one is lo develop an ALU and second is to develop the boundary scan chip. ALU is a unit or a component for a cligital circuit or a integrated circuit which is …

Litar Aritmetik Reja, Abd. Mutalib Leorna Shazerine

Student Works (2000-2009)

Projek Ilmiah Tahap Akhir II, iaitu WXES 3182 adalah suatu latihan akademik di dalam penyelidikan, rekabentuk, pembangunan dan komunikasi yang melibatkan prinsip-prinsip sains komputer. Projek WXES 3182 ini merupakan kursus pelengkap bagi pelajar-pelajar tahun akhir untuk mendapatkan penganugerahan Sarjana Muda Sains Komputer. Projek WXES 3182 ini adalah kesinabungan daripada projek WXES 3181 Kajian penyehdikan yang telah dijalankan adalah berkaitan dengan konsep sistem nombor reja dan litar aritmetik reja. Laporan latihan ilmiah tahap akhir II ini, merangkumi pembangunan projek WXES 3181 dan WXES 3182. laporan ini terdiri daripada lapan bahagian dan diantaranya ialah pengenalan kepada projek, kajian literasi, metodologi yang digunakan …

Vhdl Description For Ip Engine, Bathich Zeliall

Student Works (2000-2009)

Developing hardware support for network layer protocol processing is a very complex and demanding task. However. for optimal performance hardware acceleration can be required. To cope with the situation. this project present a high-level design approach. which targets the development of configurable and reusable components. Therefore it obtains the integration of advanced tools for the development of the IP Engine into the design environment. This process is illustrated based on a TCP/IP header analysis and validation component for which initial performance results are presented. The development of this Engine is embedded in an approach to develop flexible and configurable protocol …

Implementation And Performance Of Error Correction Codes For High-Speed Computer Networks, Jochen Spengler

Dissertations and Theses

During the transmission of data there is always a possibility that errors occur and some pieces are modified. If the receiver detects an error it either sends a request for retransmission or, like in networks using Ethernet, it does not send an acknowledgment for the erroneous frame. In this case the sender waits a certain time and retransmits the frame. With the development of faster computer networking hardware and the need for more real-time applications, these errors have become a major concern. Long retransmission latencies and the need for large memories for buffering drive the development of more reliable network …

Genetic Algorithms Vs. Simulated Annealing: A Comparison Of Approaches For Solving The Circuit Partitioning Problem, Theodore W. Manikas, James T. Cain

Computer Science and Engineering Research

An important stage in circuit design is placement, where components are assigned to physical locations on a chip. A popular contemporary approach for placement is the use of simulated annealing. While this approach has been shown to produce good placement solutions, recent work in genetic algorithms has produced promising results. The purpose of this study is to determine which approach will result in better placement solutions.

A simplified model of the placement problem, circuit partitioning, was tested on three circuits with both a genetic algorithm and a simulated annealing algorithm. When compared with simulated annealing, the genetic algorithm was found …

Investigation Of Solution Space Of Trees And Dags For Realization Of Combinational Logic In At 6000 Series Fpgas, Philip Ho

Dissertations and Theses

Various tree and Directed Acyclic Graph structures have been used for representation and manipulation of switching functions. Among these structures the Binary Decision Diagrams have been the most widely used in logic synthesis. A BDD is a binary tree graph that represents the recursive execution of Shannon's expansion. A FDD is a directed function graph that represents the recursive execution of Reed Muller expansion.

A family of decision diagrams for representation of Boolean function is introduced in this thesis. This family of Kronecker Functional Decision Diagrams (KFDD) includes the Binary Decision Diagrams (BDD) and Functional Decision Diagrams (FDD) as subsets. …

Hybrid Wafer Scale Microcircuit Integration -- [ 5008213 ], Edward S. Kolesar Jr.

AFIT Patents

A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and hose wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment …

Hybrid Wafer Scale Microcircuit Integration -- [ 4989063 ], Edward S. Kolesar Jr.

AFIT Patents

A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and host wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment …