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Articles 211 - 231 of 231

Full-Text Articles in Computer and Systems Architecture

Performance Testing An Inline Network Intrusion Detection System Using Snort, Richard Wagoner Nov 2007

Performance Testing An Inline Network Intrusion Detection System Using Snort, Richard Wagoner

Morehead State Theses and Dissertations

A thesis presented to the faculty of the College of Science and Technology at Morehead State University in partial fulfillment of the requirements for the Degree of Master of Science by Richard Wagoner on November 16, 2007.


Nesting System With Quantization And Knowledge Base Applied, Leszek Koszalka, Grzegorz Chmaj Apr 2007

Nesting System With Quantization And Knowledge Base Applied, Leszek Koszalka, Grzegorz Chmaj

Electrical & Computer Engineering Faculty Research

Nesting algorithms deal with placing two dimensional shapes on the given canvas. In this paper a binary way of solving the nesting problem is proposed. Geometric shapes are quantized into binary form, which is used to operate on them. After finishing nesting they are converted back into original geometrical form. Investigations showed, that there is a big influence of quantization accuracy for the nesting effect. However, greater accuracy results with longer time of computation. The proposed knowledge base system is able to strongly reduce the computational time.


Byzantine Fault Tolerant Coordination For Web Services Atomic Transactions, Wenbing Zhao Jan 2007

Byzantine Fault Tolerant Coordination For Web Services Atomic Transactions, Wenbing Zhao

Electrical and Computer Engineering Faculty Publications

In this paper, we present the mechanisms needed for Byzantine fault tolerant coordination of Web services atomic transactions. The mechanisms have been incorporated into an open-source framework implementing the standard Web services atomic transactions specification. The core services of the framework, namely, the activation service, the registration service, the completion service, and the distributed commit service, are replicated and protected with our Byzantine fault tolerance mechanisms. Such a framework can be useful for many transactional Web services that require high degree of security and dependability.


A Tabu Search Algorithm To Minimize The Makespan For The Unrelated Parallel Machines Scheduling Problem With Setup Times, Magdy Helal, Ghaith Rabadi, Ameer Al-Salem Jan 2006

A Tabu Search Algorithm To Minimize The Makespan For The Unrelated Parallel Machines Scheduling Problem With Setup Times, Magdy Helal, Ghaith Rabadi, Ameer Al-Salem

Engineering Management & Systems Engineering Faculty Publications

In this paper we propose a tabu search implementation to solve the unrelated parallel machines scheduling problem with sequence- and machine- dependent setup times to minimize the schedules makespan. The problem is NP-hard and finding an optimal solution efficiently is unlikely. Therefore, heuristic techniques are more appropriate to find near-optimal solutions. The proposed tabu search algorithm uses two phases of perturbation schemes: the intra-machine perturbation, which optimizes the sequence of jobs on the machines, and the inter-machine perturbation, which balances the assignment of the jobs to the machines. We compare the proposed algorithm to an existing one that addressed the …


Efficient Scheduling For Sdmg Cioq Switches, Mei Yang, S. Q. Zheng Jan 2006

Efficient Scheduling For Sdmg Cioq Switches, Mei Yang, S. Q. Zheng

Electrical & Computer Engineering Faculty Research

Combined input and output queuing (CIOQ) switches are being considered as high-performance switch architectures due to their ability to achieve 100% throughput and perfectly emulate output queuing (OQ) switch performance with a small speedup factor S. To realize a speedup factor S, a conventional CIOQ switch requires the switching fabric and memories to operate S times faster than the line rate. In this paper, we propose to use a CIOQ switch with space-division multiplexing expansion and grouped input/output ports (SDMG CIOQ switch for short) to realize speedup while only requiring the switching fabric and memories to operate at the line …


Dynamic Voltage Scaling Techniques For Power Efficient Video Decoding, Ben Lee, Eriko Nurvitadhi, Reshma Dixit, Chansu Yu, Myungchul Kim Oct 2005

Dynamic Voltage Scaling Techniques For Power Efficient Video Decoding, Ben Lee, Eriko Nurvitadhi, Reshma Dixit, Chansu Yu, Myungchul Kim

Electrical and Computer Engineering Faculty Publications

This paper presents a comparison of power-aware video decoding techniques that utilize dynamic voltage scaling (DVS). These techniques reduce the power consumption of a processor by exploiting high frame variability within a video stream. This is done through scaling of the voltage and frequency of the processor during the video decoding process. However, DVS causes frame deadline misses due to inaccuracies in decoding time predictions and granularity of processor settings used. Four techniques were simulated and compared in terms of power consumption, accuracy, and deadline misses. In addition, this paper proposes the frame-data computation aware (FDCA) technique, which is …


The Case For Thoroughly Testing Complex System Dynamic Models, Wayne Wakeland, Megan Hoarfrost Jul 2005

The Case For Thoroughly Testing Complex System Dynamic Models, Wayne Wakeland, Megan Hoarfrost

Complex Systems Faculty Publications and Presentations

In order to determine whether model testing is as useful as suggested by modeling experts, the full battery of model tests recommended by Forrester, Senge, Sterman, and others was applied retrospectively to a complex previously-published system dynamics model. The time required to carry out each type of test was captured, and the benefits that resulted from applying each test was determined subjectively. The resulting benefit to cost ratios are reported. These ratios suggest that rather than focusing primarily on sensitivity testing, modelers should consider other types of model tests such as extreme condition tests and family member tests. The study …


Programmable Process Flow Networks, Filip D. Cuckov Apr 2005

Programmable Process Flow Networks, Filip D. Cuckov

Electrical & Computer Engineering Theses & Dissertations

A model that introduces programmability to processes occurring in a cargo terminal simulation through the use of a process language is presented in this thesis. The model provides a means for a straight-forward definition, and redefinition of changing processes, their incorporation in the simulation architecture and efficient execution. The model was built to investigate a solution for transforming the cargo terminal simulation CPortS into a process-oriented simulation without hard-coded processes. The approach taken separates the system into an architecture and a set of processes which utilize and interact with the architecture's resources and infrastructure. The processes that take place within …


Unification Of Transactions And Replication In Three-Tier Architectures Based On Corba, Wenbing Zhao, Louise E. Moser, P. Michael Melliar-Smith Jan 2005

Unification Of Transactions And Replication In Three-Tier Architectures Based On Corba, Wenbing Zhao, Louise E. Moser, P. Michael Melliar-Smith

Electrical and Computer Engineering Faculty Publications

In this paper, we describe a software infrastructure that unifies transactions and replication in three-tier architectures and provides data consistency and high availability for enterprise applications. The infrastructure uses transactions based on the CORBA object transaction service to protect the application data in databases on stable storage, using a roll-backward recovery strategy, and replication based on the fault tolerant CORBA standard to protect the middle-tier servers, using a roll-forward recovery strategy. The infrastructure replicates the middle-tier servers to protect the application business logic processing. In addition, it replicates the transaction coordinator, which renders the two-phase commit protocol nonblocking and, thus, …


Power Analysis And Optimization Techniques For Energy Efficient Computer Systems, Wissam Chedid, Chansu Yu, Ben Lee Jan 2005

Power Analysis And Optimization Techniques For Energy Efficient Computer Systems, Wissam Chedid, Chansu Yu, Ben Lee

Electrical and Computer Engineering Faculty Publications

Reducing power consumption has become a major challenge in the design and operation of to-day’s computer systems. This chapter describes different techniques addressing this challenge at different levels of system hardware, such as CPU, memory, and internal interconnection network, as well as at different levels of software components, such as compiler, operating system and user applications. These techniques can be broadly categorized into two types: Design time power analysis versus run-time dynamic power management. Mechanisms in the first category use ana-lytical energy models that are integrated into existing simulators to measure the system’s power consumption and thus help engineers to …


Hierarchical Hybrid Multicast An End System Multicast Algorithm Approach, Guillermo Loaisiga Oct 2004

Hierarchical Hybrid Multicast An End System Multicast Algorithm Approach, Guillermo Loaisiga

Electrical & Computer Engineering Theses & Dissertations

Due to the rapid development in the computer and communication technologies, the Internet is experiencing an increasing demand of high-speed, real-time distributed applications, such as live streaming multimedia, videoconferencing, distributed simulations, and multiparty games. Multicast is an efficient transmission mechanism to support these applications. Historically, IP Multicast (IPM) has provided multicast support with well-known benefits, especially in bandwidth savings. However, it has experienced little deployment due to economic and architectural limitations.

Overlay multicast holds promise for the implementation of large scale Internet multicast services. An overlay network is a virtual topology constructed on top of the Internet infrastructure. This concept …


Isomorphic Strategy For Processor Allocation In K-Ary N-Cube Systems, Moonsoo Kang, Chansu Yu, Hee Yong Youn, Ben Lee, Myungchul Kim May 2003

Isomorphic Strategy For Processor Allocation In K-Ary N-Cube Systems, Moonsoo Kang, Chansu Yu, Hee Yong Youn, Ben Lee, Myungchul Kim

Electrical and Computer Engineering Faculty Publications

Due to its topological generality and flexibility, the k-ary n-cube architecture has been actively researched for various applications. However, the processor allocation problem has not been adequately addressed for the k-ary n-cube architecture, even though it has been studied extensively for hypercubes and meshes. The earlier k-ary n-cube allocation schemes based on conventional slice partitioning suffer from internal fragmentation of processors. In contrast, algorithms based on job-based partitioning alleviate the fragmentation problem but require higher time complexity. This paper proposes a new allocation scheme based on isomorphic partitioning, where the processor space is partitioned into higher dimensional isomorphic subcubes. The …


A Pipelined Architecture For Real Time Correction Of Barrel Distortion In Wide-Angle Camera Images, Hau Trung Ngo Apr 2003

A Pipelined Architecture For Real Time Correction Of Barrel Distortion In Wide-Angle Camera Images, Hau Trung Ngo

Electrical & Computer Engineering Theses & Dissertations

Images captured by wide-angle cameras show barrel type spatial distortion due to wide-angle configuration of the camera lens where image regions farther from the center are compressed in a nonlinear fashion. The barrel distortion correction technique based on least squares estimation attempts to correct a distorted image by expanding it nonlinearly so that straight lines in the object space remain straight in the image space. The intensity value of a pixel in the expanded image is calculated by back mapping its position to the corresponding position in the distorted image and performing linear interpolation on the neighboring pixels. Distorted images …


Establishing A Lan Network For Designing And Analyzing Of Manufacturing Products, Yuqiu You Apr 2002

Establishing A Lan Network For Designing And Analyzing Of Manufacturing Products, Yuqiu You

Morehead State Theses and Dissertations

A thesis presented to the faculty of the College of Science & Technology at Morehead State University in partial fulfillment of the requirements for the Degree of Master of Science by Yuqiu You in Spring of 2002.


Implementation And Performance Of Error Correction Codes For High-Speed Computer Networks, Jochen Spengler Sep 1999

Implementation And Performance Of Error Correction Codes For High-Speed Computer Networks, Jochen Spengler

Dissertations and Theses

During the transmission of data there is always a possibility that errors occur and some pieces are modified. If the receiver detects an error it either sends a request for retransmission or, like in networks using Ethernet, it does not send an acknowledgment for the erroneous frame. In this case the sender waits a certain time and retransmits the frame. With the development of faster computer networking hardware and the need for more real-time applications, these errors have become a major concern. Long retransmission latencies and the need for large memories for buffering drive the development of more reliable network …


An Empirical Comparison Of Area-Universal And Other Parallel Computing Networks, Ronald I. Greenberg, Lee Guan Sep 1996

An Empirical Comparison Of Area-Universal And Other Parallel Computing Networks, Ronald I. Greenberg, Lee Guan

Computer Science: Faculty Publications and Other Works

This paper provides empirical comparison of the communication capabilities of two area-universal networks, the fat-tree and the fat-pyramid, to the popular mesh and hypercube networks for parallel computation. While area-universal networks have been proven capable of simulating, with modest slowdown, any computation of any other network of comparable area, prior work has generally left open the question of how area-universal networks compare to other networks in practice. Comparisons are performed using techniques of throughput and latency analysis that have previously been applied to k-ary n-cube networks and using various existing models to equate the hardware cost of the networks being …


Acoustic Correlates Of Vowel Perception As Determined From Synthesis Experiments With Multi-Tone Stimuli, Zhongjiang Zhang Oct 1993

Acoustic Correlates Of Vowel Perception As Determined From Synthesis Experiments With Multi-Tone Stimuli, Zhongjiang Zhang

Electrical & Computer Engineering Theses & Dissertations

An essential requirement of speech signal processing is to extract information (features or parameters) from the speech signal which encode the information carried by the signal. The objective of this thesis work was to examine and evaluate two feature sets as acoustic correlates for vowel perception. They are formants and DCTCs. Formants are the frequencies of spectral peaks of the speech signal. DCTCs are the Discrete Cosine Transform Coefficients of the magnitude spectrum and are thus features which encode the global spectral shape of speech signal.

There are different opinions regarding which feature set is a more accurate representation for …


A Systolic Simulation And Transformation System, Ronald I. Greenberg, H.-C. Oh Mar 1993

A Systolic Simulation And Transformation System, Ronald I. Greenberg, H.-C. Oh

Computer Science: Faculty Publications and Other Works

This paper presents a CAD tool, SystSim, to ease the design of systolic systems. Given a high-level, functional description of processors, and a high-level description of their interconnection, SystSim will perform simulations and provide graphical output. SystSim will also perform transformations such as retiming, which eases use of the methodology of Leiserson and Saxe of designing a system with broadcasting and then obtaining a systolic system through retiming.


Parallel Architectures For Solving Combinatorial Problems Of Logic Design, Phuong Minh Ho Jan 1989

Parallel Architectures For Solving Combinatorial Problems Of Logic Design, Phuong Minh Ho

Dissertations and Theses

This thesis presents a new, practical approach to solve various NP-hard combinatorial problems of logic synthesis, logic programming, graph theory and related areas. A problem to be solved is polynomially time reduced to one of several generic combinatorial problems which can be expressed in the form of the Generalized Propositional Formula (GPF) : a Boolean product of clauses, where each clause is a sum of products of negated or non-negated literals.


Randomized Routing On Fat-Trees, Ronald I. Greenberg Oct 1985

Randomized Routing On Fat-Trees, Ronald I. Greenberg

Computer Science: Faculty Publications and Other Works

Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda+lgnlglgn) with probability 1-O(1/ …


Systems Reliability Using The Flow Graph, Kenneth Edward Farrier Jan 1970

Systems Reliability Using The Flow Graph, Kenneth Edward Farrier

Dissertations and Theses

The problem of calculating the reliability of a complex system of interacting elements is delineated to a linear system, no element of the system having a reliability distribution in terms of any other e1ement of the system, where only one path is taken through the system at a time. A precise definition is then developed to specify the reliability of the linear, single path at a time, system. A precise and concise generating function is found that effortlessly produces the reliability of the linear, single path at a time, system directly from the reliability flew graph of the system.