Open Access. Powered by Scholars. Published by Universities.®

Computer Engineering Commons™

Open Access. Powered by Scholars. Published by Universities.®

Theses and Dissertations

Discipline
Institution
Keyword
Publication Year

Articles 691 - 720 of 728

Full-Text Articles in Computer Engineering

Object-Oriented Analysis, Design, And Implementation Of The Saber Wargame, David S. Douglass Dec 1992

Object-Oriented Analysis, Design, And Implementation Of The Saber Wargame, David S. Douglass

Theses and Dissertations

Saber is a two-sided, air and land war game that simulates decisions made of commanders at the theater-level. It is being developed by the Air Force Institute of Technology for the Air Force Wargaming center at Maxwell AFB, Alabama. Saber models conventional, chemical, and nuclear warfare between aggregated air and land forces. It also portrays the effects of logistics, satellites, weather, terrain, and intelligence which add to the realism of the Saber war game. The Saber war game has three main components, the preprocessor. which is responsible for scenario development and pregame activities, the simulation. the guts of the war …

Go to article

A Vhdl Interpreter For Model-Based Diagnoses, David R. Griffin Dec 1992

A Vhdl Interpreter For Model-Based Diagnoses, David R. Griffin

Theses and Dissertations

Model-based reasoning permits diagnostic applications to be written without waiting for someone to become an 'expert' of the system. For model-based diagnostics, there must be a model to reason from. This thesis explores using a VHDL description of the system as that model. A system based around a VHDL interpreter was written specifically for a model-based diagnostic algorithm. Currently, the diagnostic system uses an algorithm by Dries. This algorithm was derived from Scarl's Full Consistency Algorithm. The system was designed to be modular so that different diagnostic techniques could be implemented. It is divided into three parts: a VHDL parser, …

Go to article

Solution To A Multicriteria Aircraft Routing Problem Utilizing Parallel Search Techniques, James J. Grimm Iii Dec 1992

Solution To A Multicriteria Aircraft Routing Problem Utilizing Parallel Search Techniques, James J. Grimm Iii

Theses and Dissertations

Pilots select routes based on factors such as threats, fuel, time on target, distance, and refueling points. This is a time consuming task. This thesis presents the software engineering synthesis of a software tool, based on a parallelized A* search algorithm, to select routes. For simplicity only threats and distance are used. A centralized open list is used with one processor managing the list while the other processors perform the node expansions. This decomposition result in a dynamically load balanced system. A number of parameters are changed to study their impact on the execution time. The use of a branch …

Go to article

Creating And Manipulating Formalized Software Architectures To Support A Domain-Oriented Application Composition System, Cynthia G. Anderson Dec 1992

Creating And Manipulating Formalized Software Architectures To Support A Domain-Oriented Application Composition System, Cynthia G. Anderson

Theses and Dissertations

This research investigated technology which enables sophisticated users to specify, generate, and maintain application software in domain-oriented terms. To realize this new technology, a development environment, called Architect, was designed and implemented. Using canonical formal specifications of domain objects, Architect rapidly composes these specifications into a software application and executes a prototype of that application as a means to demonstrate its correctness before any programming language specific code is generated. Architect depends upon the existence of a formal object base (or domain model) which was investigated by another student in related research. The research described in this thesis relied on …

Go to article

An Intelligent Real-Time System Architecture Implemented In Ada, Michael A. Whelan Dec 1992

An Intelligent Real-Time System Architecture Implemented In Ada, Michael A. Whelan

Theses and Dissertations

Conventional real-time systems are fully deterministic allowing for off-line, optimal, task scheduling under all circumstances. Real-time intelligent systems add non-deterministic task execution times and non- deterministic task sets for scheduling purposes. Non-deterministic task sets force intelligent real-time systems to trade-off execution time with solution quality during run-time and perform dynamic task scheduling. Four basic design considerations addressing those tradeoffs have been identified: control reasoning, focus of attention, parallelism, and algorithm efficacy. Non-real- time intelligent systems contain an environment sensor, a model of the environment, a reasoning process, and a large collection of procedural processes. Real-time intelligent systems add to these …

Go to article

Design And Development Of A High-Speed Winograd Fast Fourier Transform Processor Board, James F. Herron Dec 1992

Design And Development Of A High-Speed Winograd Fast Fourier Transform Processor Board, James F. Herron

Theses and Dissertations

Since 1985, the Air Force Institute of Technology has pursued a project to develop a 4080-point Discrete Fourier Transform processor using the Winograd Fourier Transform Algorithm (WFTA) and Good-Thomas Prime Factoring Algorithm (PFA). In the first attempt to build a working system, this research effort designed and constructed, in part, a modified single processor architecture in order to demonstrate the proof of concept of the WFTA system design. This prototype architecture is simpler in implementation but uses the same principles and procedures as those of the 4080-point WFTA design. The design developed in this thesis was validated using the Very …

Go to article

Satcom General Purpose Modem Dscs Iii Sct Beacon Telemetry Display, James D. Coppola Dec 1992

Satcom General Purpose Modem Dscs Iii Sct Beacon Telemetry Display, James D. Coppola

Theses and Dissertations

This thesis documents the design and implementation of a DSCS III single Channel Transponder (SCT) beacon telemetry display. The system is a personal computer based design which interfaces to three SCT beacon receiver/demodulators. The software was designed to decode and display both the DSCS III A and DSCS HI B satellite beacons. Recordings of the SCT beacon display can be made on paper and/or magnetic media when triggered by the user, a watchdog timer, or the SCT command accept telemetry bit. In addition, the system can be configured with an IRIG B Universal Time Coordinates (UTC) card which enables the …

Go to article

Formalizing, Validating, And Verifying Real-Time System Requirements With Reacto And Vhdl, Frank C. Young Dec 1992

Formalizing, Validating, And Verifying Real-Time System Requirements With Reacto And Vhdl, Frank C. Young

Theses and Dissertations

We develop a methodology for formalizing, verifying, and validating the requirements specification of real-time systems based on a graphical and formal hierarchical Finite State Machine (FSM) language Reacto. We define a means to quantify time and express real-time constraints in Reacto and a transformation from Reacto to the Very High Speed Integrated Circuit (VHSIC) hardware Description Language (VHDL). Reacto's high level abstractions, graphical nature, and theorem prover produce efficient, accurate, and easily understood specifications. We use VHDL's event driven simulation capability, concurrency, and temporal operators to thoroughly examine temporal dependencies between the state machine transitions, and to increase simulation power …

Go to article

An Investigation Of Structural Locality In The Memory Referencing Behavior Of Computer Programs, Michael E. Bletzinger Dec 1992

An Investigation Of Structural Locality In The Memory Referencing Behavior Of Computer Programs, Michael E. Bletzinger

Theses and Dissertations

The nature of structural locality as defined by same stack distance access is investigated in this thesis. The question is whether structural locality can be characterized as an inherent type of behavior. The results revealed that structural locality is strongly influenced by a program's design and phase of execution. Entropy measurements revealed that the predictiveness of structural locality is also influenced by program design. A Markov model was refined to capture the characteristics of structural locality that were measured. Trace synthesis demonstrated some success in reproducing same stack distance run distributions when the model had enough states to encompass the …

Go to article

Computer Simulation Of A General Purpose Satellite Modem, William L. Montgomery Jr. Dec 1992

Computer Simulation Of A General Purpose Satellite Modem, William L. Montgomery Jr.

Theses and Dissertations

The purpose of this research was to model and simulate the performance of a digital phase shift keyed satellite modem. The probability of bit error (P sub b) at different levels of energy per bit to noise power ratio (E sub b/N sub o) was the performance measure. The channel was assumed to contribute only additive white Gaussian noise. A second order Costas loop performs demodulation in the modem and was the key part of the simulation. The Costas loop with second order Butterworth arm filters was tested by finding the response to a phase or frequency step. The Costas …

Go to article

Generalization And Parallelization Of Messy Genetic Algorithms And Communication In Parallel Genetic Algorithms, Laurence D. Merkle Dec 1992

Generalization And Parallelization Of Messy Genetic Algorithms And Communication In Parallel Genetic Algorithms, Laurence D. Merkle

Theses and Dissertations

Genetic algorithms (GA) are highly parallelizable, robust semi- optimization algorithms of polynomial complexity. The most commonly implemented GAs are 'simple' GAs (SGAs). Reproduction, crossover, and mutation operate on solution populations. Deceptive and GA-hard problems are provably difficult for simple GAs. Messy GAs (MGA) are designed to overcome these limitations. The MGA is generalized to solve permutation type optimization problems. Its performance is compared to another MGA's, an SGA's, and a permutation SGA's. Against a fully deceptive problem the generalized MGA (GMGA) consistently performs better than the simple GA. Against an NP-complete permutation problem, the GMGA performs better than the other …

Go to article

Development Of A Protocol Usage Guideline For Conservative Parallel Simulations, Prescott J. Van Horn Dec 1992

Development Of A Protocol Usage Guideline For Conservative Parallel Simulations, Prescott J. Van Horn

Theses and Dissertations

The objective of distributed simulation is to speedup simulation execution by partitioning the simulation processing load over multiple processors, This thesis reviews current synchronization protocol methods for distributed simulations, and proposes guidelines for obtaining optimal conservative simulation partitionings using empirical evidence. An analysis is performed using three protocol variations of the Chandy-Misra HULL message algorithm, two using a pending message blocking strategy, and the other using a safetime blocking strategy. A fourth protocol evaluated is based on the SRADS algorithm proposed by Reynolds. The analysis involves a study of all possible 2 and 4 node configurations, for three queuing simulations, …

Go to article

Parallel Simulation Of Structural Vhdl Circuits On Intel Hypercubes, Thomas A. Breeden Dec 1992

Parallel Simulation Of Structural Vhdl Circuits On Intel Hypercubes, Thomas A. Breeden

Theses and Dissertations

Many VLSI circuit designs are too large to be simulated with VHDL in a reasonable amount of time. One approach to reducing the simulation time is to distribute the simulation over several processors. This research creates an environment for designing and simulating structural VHDL circuits on the Intel iPSC/2 and iPSC/860 Hypercubes. Logic gates and system behaviors are partitioned among the processors, and signed changes are shared via event messages. Circuit simulations are run over the SPECTRUM parallel simulation testbed, and the null- message paradigm is used to avoid deadlock. Structural circuits ranging from forty to over one thousand logic …

Go to article

Implementation And Analysis Of Np-Complete Algorithms On A Distributed Memory Computer, Joel S. Garmon Mar 1992

Implementation And Analysis Of Np-Complete Algorithms On A Distributed Memory Computer, Joel S. Garmon

Theses and Dissertations

The purpose of this research is to explore methods used to parallelize NP-complete problems and the degree of improvement that can be realized using different methods of load balancing. A serial and four parallel A* branch and bound algorithms were implemented and executed on an Intel iPSC/2 hypercube computer. One parallel algorithm used a global, or centralized, list to store unfinished work and the other three parallel algorithms used a distributed list to store unfinished work locally on each processor. the three distributed list algorithms are: without load balancing, with load balancing, and with load balancing and work distribution. The …

Go to article

Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec Mar 1992

Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec

Theses and Dissertations

The minimization of logic circuits has been an important area of research for more than a half century. The approaches taken in this field, however, have for the most part been ad hoc. Boolean techniques have been employed to manipulate formulas, but not to perform symbolic reasoning. Boolean equations are employed principally as icons; they are never solved. The first objective of this dissertation is to apply Boolean reasoning systematically and uniformly to the minimization problem. Boolean reasoning entails the reduction of systems of Boolean equations to a single equation; the single equation is an abstraction, independent of the form …

Go to article

Logic Programming In Digital Circuit Design, Joseph W. Eicher Dec 1991

Logic Programming In Digital Circuit Design, Joseph W. Eicher

Theses and Dissertations

The design of large, complex digital circuitry requires highly skilled engineers. Much of the time spent by these engineers in the design phase involves tasks that are repetitive, tedious, and slow. If these repetitive tasks are automated, the engineer can spend more time managing the design process and produce a better-quality design in less time. Logic programming can be used to automate design tasks, even those that require a high degree of skill. This thesis investigates several aspects of the digital circuit design process that involve pattern-matching paradigms suitable for encoding in the logic programming language Prolog.

Go to article

Frequency Domain Speech Coding, Shane Switzer Dec 1991

Frequency Domain Speech Coding, Shane Switzer

Theses and Dissertations

The major goal of this research was to investigate speech coding techniques in an attempt to achieve high quality speech transmittable at 4800 bits per second. The approach taken to achieve this goal was to code the frequency domain representation of speech. Speech was represented by a sparse set of frequency components. Four frequency selections schemes were implemented, and the resulting frequency coefficients (magnitude and phase) were coded in an efficient manner for transmission. Specific techniques involved in the speech coder included: (1) a recurrent neural architecture to make a periodic/noiselike decision, (2) the use of variable length windows for …

Go to article

Formal Verification Of Digital Logic, Stuart L. Labovitz Dec 1991

Formal Verification Of Digital Logic, Stuart L. Labovitz

Theses and Dissertations

The most widely used technique for checking the correctness of digital circuits designs is simulation. As the complexity of digital circuits has continued to grow, however, circuit designers have become unable to perform complete simulations of their integrated circuits. Formal hardware verification provides an alternative approach, performing a series of mathematical proofs in order to show that the construction of the circuit from its submodules will result in the intended overall circuit behavior. Papers by Barrow in 1983 and 1984 discuss a PROLOG-based hierarchical formal circuit verification system named VERIFY. AFIT VERIFY, a simple, experimental reverse-engineered version of Barrow's VERIFY …

Go to article

Requirements Analysis For A Hardware, Discrete-Event, Simulation Engine Accelerator, Paul J. Taylor Jr. Dec 1991

Requirements Analysis For A Hardware, Discrete-Event, Simulation Engine Accelerator, Paul J. Taylor Jr.

Theses and Dissertations

An analysis of a general Discrete Event Simulation (DES), executing on the distributed architecture of an eight mode Intel PSC/2 hypercube, was performed. The most time consuming portions of the general DES algorithm were determined to be the functions associated with message passing of required simulation data between processing nodes of the hypercube architecture. A behavioral description, using the IEEE standard VHSIC Hardware Description and Design Language (VHDL), for a general DES hardware accelerator is presented. The behavioral description specifies the operational requirements for a DES coprocessor to augment the hypercube's execution of DES simulations. The DES coprocessor design implements …

Go to article

Implementation Of An Object-Oriented Flight Simulator D.C. Electrical System On A Hypercube Architecture, Guy R. Booth Dec 1991

Implementation Of An Object-Oriented Flight Simulator D.C. Electrical System On A Hypercube Architecture, Guy R. Booth

Theses and Dissertations

The Software Engineering Institute developed an Object-Oriented Paradigm for Flight Simulators based on the concept of mapping the behavior of physical objects from an aircraft into an object-oriented software architecture. This mapping is a semi-formal method that maps objects to a hierarchy that has three logical layers: objects, systems, and executives. The paradigm was developed with the idea of implementing the derived simulation design on a parallel or distributed computer architecture, but no explicity design features are provided for implementing the design on a parallel computer. This research addresses the issue of determining what extensions (if any) are required to …

Go to article

Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau Dec 1991

Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau

Theses and Dissertations

VHDL models are executed sequentially in current commercial simulators. As chip designs grow larger and more complex, simulations must run faster. One approach to increasing simulation speed is through parallel processors. This research transforms the behavioral and structural models created by Intermetrics' sequential VHDL simulator into models for parallel execution. The models are simulated on an Intel iPSC/2 hypercube with synchronization of the nodes being achieved by utilizing the Chandy Misra paradigm for discrete-event simulations. Three eight-bit adders, the ripple carry, the carry save, and the carry-lookahead, are each run through the parallel simulator. Simulation time is cut in at …

Go to article

Electrically Erasable Programmable Integrated Circuits For Replacement Of Obsolete Ttl Logic, Joseph V. Breen Dec 1991

Electrically Erasable Programmable Integrated Circuits For Replacement Of Obsolete Ttl Logic, Joseph V. Breen

Theses and Dissertations

Two microcircuits with electrically erasable programmable logic arrays, which use Fowler-Nordheim (F-N) tunneling for both programming and erasing, were designed to demonstrate the use of programmable logic for obsolete TTL logic replacement. Each microcircuit was fabricated in the Orbit 2-micron double-poly low noise analog CMOS process through MOSIS. Software to generate VHDL structural models from a pin list was developed and the logic of both designs was verified by simulation using the Zycad VHDL simulator. The first microcircuit included a simple programmable logic circuit and test cells that allowed measurement of the programming characteristics of the floating gate transistors. Test …

Go to article

Speech Recognition Using Multiple Features And Multiple Recognizers, Thomas F. Rathbun Dec 1991

Speech Recognition Using Multiple Features And Multiple Recognizers, Thomas F. Rathbun

Theses and Dissertations

The purpose of this thesis is to demonstrate the feasibility of using multiple features and multiple recognizers to perform isolated word recognition. This is accomplished by performing multiple independent recognition tests and fusing the results together to get a single recognition result. The speech data is recorded and each word is extracted into a separate file. Eight features are calculated for each word. The features are calculated on 512 sample time slices and produce 16 component vector output. The three recognizers use the eight features to produce a total of 24 error distance lists. These lists are then fused together …

Go to article

The Application Of Statistical Estimation Techniques To Terrain Modeling, Donald P. Duckett Jr. Dec 1991

The Application Of Statistical Estimation Techniques To Terrain Modeling, Donald P. Duckett Jr.

Theses and Dissertations

This thesis researches methods of generating accurate and realistic polygonal terrain models by reducing gridded sampled terrain elevation data such as DMA DTED. The terrain models generated should be applicable for use in flight simulators and other systems. Existing methods of terrain modeling are discussed, and limitations of these systems are presented. The geostatistical estimation technique known as kriging is presented as a method estimating terrain elevations at locations not provided in DMA DTED or other gridded terrain elevation data. Kriging is an optimal interpolation method based on statistical analysis of the data. It also provides a measure of accuracy, …

Go to article

A Standardized Software Reliability Measurement Methodology, Joseph J. Stanko Dec 1991

A Standardized Software Reliability Measurement Methodology, Joseph J. Stanko

Theses and Dissertations

Current Air Force practice is to perform Operational Test and Evaluation (OT and E) for each new weapons system. In support of this, Headquarters Air Force Operational Test and Evaluation Center (HQ AFOTEC) is responsible for measuring both suitability and effectiveness. While suitability is adequately measured, the current effort only addresses hardware effectiveness, or at best, system effectiveness. Since tools and metrics are in place for software suitability assessments related to OT and E (for example, software maintainability), there should be some effective way of measuring the operational effectiveness of software. Currently, HQ AFOTEC/LG5 has a data collection tool for …

Go to article

A Prolog-Based System For Hardware Verification, Kevin L. Sparks Mar 1991

A Prolog-Based System For Hardware Verification, Kevin L. Sparks

Theses and Dissertations

With the expanding number of components provided on a single digital chip, verification of digital designs is becoming a major problem. The more circuits one places on a single chip, the greater the number of input/output combinations which need to be checked. A paper by Barrow in 1984 discusses a Prolog-based hierarchical formal verification system which he calls VERIFY. Barrow provided a lot of information on what VERIFY can and cannot do, and on projected enhancements. He does not, however, mention how VERIFY actually performs the task of formal verification. This thesis will provide a description of one possible implementation …

Go to article

A Common Interface Real-Time Multiprocessor Operating System For Embedded Systems, Michael S. Rottman Mar 1991

A Common Interface Real-Time Multiprocessor Operating System For Embedded Systems, Michael S. Rottman

Theses and Dissertations

Large real time applications such as aerospace avionics systems, battle management, and factory automation place many demands and constraints on the computing system not found in other applications. Software development is hindered by software dependence on the computer architecture and the lack of portability between systems. This thesis specifies and designs a real time multiprocessor operating system (RTMOS) that implements a consistent programming model, enabling the development of real time parallel software independent of the target architecture. The RTMOS defines the core functionality required to demonstrate the programming model. The RTMOS functional requirements are specified using Structured Analysis and Design …

Go to article

Optimal Iterative Task Scheduling For Parallel Simulations, Joann M. Sartor Mar 1991

Optimal Iterative Task Scheduling For Parallel Simulations, Joann M. Sartor

Theses and Dissertations

The ultimate purpose of this research is to reduce the time needed for execution of parallel computer simulations. In particular, the impact of task assignment strategies is determined for parallel VHDL circuit simulations. The classical scheduling problem, which assigns n precedence-constrained tasks to m processors is NP-complete in all but the simplest cases. The problem of assigning simulation tasks is further complicated by the iterative nature of computer simulations: each task is required to execute multiple times as the simulation executes. This investigation develops a polynomial-time algorithm (the level strategy) which provides optimal assignment for iterative systems with specific constraints. …

Go to article

Multiple Input Node Dataflow Processor Architecture, Gokhan Kuru Jan 1991

Multiple Input Node Dataflow Processor Architecture, Gokhan Kuru

Theses and Dissertations

A new dataflow concept, Multiple Input Node is introduced to overcome the performance and efficiency degradation problems that exist in the current dataflow computation models where the computation unit, node, accepts 2 tokens at a time. Multiple Input Node is a new computation node which has 4 inputs, hence it can accept up to 4 token packets at a time. It can perform any simple arithmetic operation or combination of operations on these 4 input tokens. It is represented by a single instruction and performs the operations in a single instruction execution. This unique Multiple Input Node architecture reduces the …

Go to article

Multi-Input Multi-Output Flight Control System Design For The Yf-16 Using Nonlinear Qft And Pilot Compensation, Russell B. Miller Dec 1990

Multi-Input Multi-Output Flight Control System Design For The Yf-16 Using Nonlinear Qft And Pilot Compensation, Russell B. Miller

Theses and Dissertations

Nonlinear Quantitative Feedback Theory (QFT) and pilot compensation techniques are used to design a 2x2 flight control system for the YF-16 aircraft over a large range of plant uncertainty. The design is based on numerical input- output time histories generated with a FORTRAN implemented nonlinear simulation of the YF-16. The first step of the design process is the generation of a set of equivalent linear time-invariant (LTI) plant models to represent the actual nonlinear plant. It has been proven that the solution to the equivalent plant problem is guaranteed to solve the original nonlinear problem. Standard QFT techniques are then …

Go to article

First Prev Next Last