Engineering Commons^™

Intrafield Distortion Characterization, Brian Martinick

Journal of the Microelectronic Engineering Conference

Distortion of printed photoresist patterns exists in all photolithographic tools and can be generated by numerous factors. These noncorrectable overlay errors are the direct result of lens imperfections, machine inaccuracy, and reticle error. Any one of these factors can have extreme effects on pattern placement and quality. This study involved characterizing this anomaly and was the first of its kind at the Semiconductor & Microsystems Fabrication Laboratory (SMFL). Incorporating a unique test reticle, crosshairs were printed on silicon wafers. These features were measured via Manufacturing Electron Beam Exposure System (MEBES) market analysis to reveal any pattern migration. This analysis involves …

Design, Fabrication, And Testing Of Crystalline Silicon Source/ Drain Finfets, Jesse J. Siman

Journal of the Microelectronic Engineering Conference

Crystalline silicon source/drain FInFET structures were designed, fabricated, and tested at the RIT Semiconductor & Microsystems Fabrication Laboratory (SMFL). Process development was completed using hand calculations, simulations, and similar processing techniques based upon mature RIT semiconductor manufacturing processes. The design under investigation is a dog-bone structure fabricated on SOT substrates. The crystalline silicon source/drain FinFETs exhibited a field effect behavior for all transistor sizes fabricated, however the smaller 1μm FinFETs were more susceptible to background noise. The smallest device, a 1x2μm FInFET yielded V_T=1.53V and a drive current of 510 μA with V_G=5V. The largest device, …

Raised Polysilicon Source / Drain Finfet Fabrication, Christopher T. Harvey

Journal of the Microelectronic Engineering Conference

The F1nFET is a novel transistor that is fabricated using silicon on insulator (SOl) technology. The body of the transistor is etched out of the top layer of silicon. The device’s polysilicon source I drain are deposited. The gate is self-aligned to the source drain. Contact cuts are made and metal is etched and patterned. The devices did not show field effect as anticipated. Analysis suggested breakdown of the gate oxide.

Analog Ic Design And Fabrication, James Tom

Journal of the Microelectronic Engineering Conference

The purpose of this project was to test the performance of analog integrated circuits and to characterize the MOSFET SPICE parameters. The data that can be obtained from this testing can be helpful for further research in the area of Analog IC design. The Semiconductor & Microsystems Fabrication Laboratory (SMFL) is a constantly evolving facility, with equipment constantly entering and leaving the lab. The process technology used was the RIT Subμ-CMOS Process, a vehicle used to teach students about process integration, semiconductor manufacturing, and the effects of process technology and device operation. Therefore, the Sub-Micron process must adapt to changes …

Development Of Silicon Nitride Etch Process, Robin Catalano

Journal of the Microelectronic Engineering Conference

Silicon nitride has been extensively used as a hard mask for the local oxidation of silicon (LOCOS) for the processing of CMOS devices. Plasma etching is an ideal etch process for patterning the silicon nitride. An optimized etch process was developed for silicon nitride using the LAM-490 plasma etcher. A designed experiment was created, executed, and analyzed. The parameters investigated were SF₆ flow, He flow, pressure, power, and electrode gap. The responses examined were silicon nitride uniformity, silicon nitride etch rate, silicon nitride to oxide selectivity and silicon nitride to photoresist selectivity. Through analysis of the experimental results optimal …

Silicon Dry Etch Process For Shallow Trench Isolation, Nathaniel Langdon

Journal of the Microelectronic Engineering Conference

Shallow Trench Isolation (STI) holds many advantages to that of its predecessor isolation technology in that STI increases the packing density, has superior latch-up immunity, smaller channel-width encroachment, and better planarity, allowing for smaller and thus faster and/or less power hungry devices. The goal of this project was to develop an anisotropic silicon etch process for use in the Drytek Quad 482 Reactive Ion Etch system, yielding a depth of at least 0.5μm and steep sidewall angle of the trench. For this study, varying plasma chemistries of consisting sulfur hexafluoride, oxygen and argon are examined to etch the bulk silicon …

Development Of A Pecvd Tetraethylorthosilicate (Teos) Fill Process For Shallow Trench Isolation, Erik P. Dolatowski

Journal of the Microelectronic Engineering Conference

As transistors have decreased in size and increased in packing density, a need has arisen for an alternative to the LOCOS method of isolation. Shallow trench isolation (STI) offers superior packing density and stronger immunity to latch up with other side benefits. A TEOS oxide fill for STI is a good choice because its mobile chemical precursors offer a high level of conformality. A plasma enhanced deposition of this oxide allows for greater control over film characteristics. A designed experiment was created to examine the effects of temperature, RF power, and substrate position (measured through electrode spacing) on the oxide …

Copper Gate Mos Capacitors Utilizing Chemical-Mechanical Planarization, Luc Dupre

Journal of the Microelectronic Engineering Conference

Applying chemical mechanical planarization techniques to form the gate for a Cu/Ti/SiO₂/Si capacitor stack has shown to be a viable alternative to conventional etching techniques used in the fabrication of MOS devices. Furthermore, it is reported that CMP does not compromise the integrity of the dielectric nor does it have an adverse affect on device performance.

Fabrication And Characterization Of Silicon Nitride Sacrificial Replacement Gate Technology, Elias Mohammad Ullah

Journal of the Microelectronic Engineering Conference

Silicon Nitride (Si₃N₄) sacrificial replacement gate were fabricated using the nitride cast method. The purpose of the Si₃N₄ cast was to develop a stand-in gate, which is then replaced by metal after source/drain formation. The technique was developed by using hot phosphoric acid etch (at 160 ° C) to form nitride cast. The phosphoric acid has nitride etch rate of about 4nm/min and good selectivity over oxide and good uniformity over silicon. A cross sectional analysis was done to view process steps.

Fabrication Of Interdiffused Dual Work Function Metal Gate Cmos Capacitors, Michael Meagher

Journal of the Microelectronic Engineering Conference

Metal gate CMOS capacitors were formed using a metal interdiffusion process at RIT. First silicon dioxide was grown on the wafer. The first metal, titanium, was deposited. Then the second metal, nickel, was deposited. The nickel was selectively etched away from the top of half the capacitors to form the different work function regions. The wafers were then heated so that the nickel diffused into the titanium. The work function could not be determined of the metal gates because the MOS capacitors did not function correctly. The capacitance stayed constant across the allowable gate voltage. This is likely due to …

Low Energy Ion Implant Capabilities At Rit, Brian J. Miga

Journal of the Microelectronic Engineering Conference

With the ever-decreasing size of device geometries today, all aspects of processing must allow for proper scaling of device parameters including junction depths. Currently in industry this challenge is met with ultra-low-energy ion implants combined with rapid thermal annealing to create the necessary profiles. It is also important to have good uniformity and throughput in order for the process to be acceptable in a manufacturing environment. Since the installation of RIT’s Varian 350D last year, there have been no implants performed at less than 3OKeV. In order to develop future processes for the student-run factory and open research possibilities, ion …

0.5 Μ Nmos Devices: Process And Fabrication, Sean Houlihan

Journal of the Microelectronic Engineering Conference

The purpose of this paper is to describe the design and the process used to fabricate NMOS devices. The goal of the experiment was to design and build the smallest NMOS transistor that has been fabricated in the SMLF manufacturing facility. A NMOS transistor is short for n-channel metal oxide silicon field effect transistor (NMOSFET or NMOS). NMOS uses electrons as the majority carrier, a major advantage in terms of device speed. The educational reasons for doing this experiment is to prove the viability of the Canon, being able to complete multi-layer aligning and to increase RIT’s ability to process …

Electron Injection By Means Of A Ballistic Source, Erik M. Wheeler

Journal of the Microelectronic Engineering Conference

The need for more robust micro electro-mechanical systems (MEMS) devices is greatly increasing. But, along with new technologies come problems, which need to be addressed. One of the more important problems is stiction. Stiction is the strong interfacial adhesion present between contacting crystalline microstructure surfaces. This often causes many MEMS devices to fail. A new method of overcoming stiction has been disclosed. Electrons are stored at the interface between silicon dioxide and silicon nitride to create a force when an external applied electric field is applied to a MEMS component containing the stored charge. The purpose of this project was …

Micromechanical Optical Modulator, Matt Shepard

Journal of the Microelectronic Engineering Conference

A novel device was designed and fabricated using Microelectronic and Microeletromechanical systems (MEMS) process procedures. The device was designed to modulate a known wavelength of light using antireflective properties. The mask design was laid out in IC Design portion of Mentor Graphics software package. Device lengths ranging from l5Oum to 300um in length were created including different orientations of etch holes designed for the removal of the sacrificial material. Theoretical modeling of the device, including the applied voltage vs. beam deflection was performed using two-dimensional Fortran program. The result indicates that the smaller devices require a larger amount of voltage …

Micro Shutters On Quartz Substrate, Vimalan Rajalingam

Journal of the Microelectronic Engineering Conference

Micro shutters are micro mechanical devices that fulfill optical and/or electrical functions. The use of such devices has gained momentum in the recent years as their minute size and high speed are viewed to be advantageous for use as optical or electrical switches. The particular type of device targeted in this project is generally referred to as a micro-actuator. It is a device that is curled in its natural state and uncurls when an external voltage is applied to it. When a transparent plate (E.g.: quartz substrate) containing thousands of such shutters can be inserted in a telescope for example, …

Incorporation Of Spc Charts Into Mesa For The Subμ-Cmos Process, Kautilya Sachdeva

Journal of the Microelectronic Engineering Conference

In a manufacturing process environment, It is important to have precise control over all of the steps involved in making the final product. The device yield goes down when the tools go out of specification. This is where the use statistical process control (SPC) charts, aids in the improvement of the entire manufacturing process. SPC charts help by letting the engineer for the tools understand whether the process is resulting in mean of the data that is higher away from the target or vice-versa (is the data reaching the upper control limit or lower control limit). The project explains the …

Integration Of Low-K Dielectric With Copper, Deoram Persaud

Journal of the Microelectronic Engineering Conference

As VLSI technologies advance, they closely follow Moore’s Law where devices are scaled down to smaller dimensions. Their performances, however are limited by the interconnect system. Introducing a low k dielectric material as an inter-metal dielectric brings a major contribution to the device’s performance improvement. With the advent of Chemical Mechanical Polishing (CMP), copper has become an ideal metal for interconnect layers. It not only lowers resistance, but also when incorporated with a low k dielectric, it lowers capacitance, thus producing a higher conductivity. Using the environmentally compliant low k dielectric material Flowable Oxide (Fox®-17), which was generously donated by …

Design And Fabrication Of A Micromechanical Pressure Sensor, Neal V. Lafferty

Journal of the Microelectronic Engineering Conference

A Microelectromechanical (MEMS) pressure sensor was designed, fabricated, and tested. Photomasks were designed for the project and built in house at RIT. The masks included designs for three separate device designs: devices to be fabricated with a KOH bulk etch, devices to be fabricated with an Surface Technology Systems (STS) Deep Reactive Ion Etch (DRIE), and a third set of scaled device designs for use with the STS DRIE process. Devices were tested in house, and the ideal design was determined. The most sensitive device, which had a resistor L/W of 10, demonstrated a voltage differential of 39 mV.

Fall/Winter 2002, 90.9 Wmpg Fm

WMPG Program Guides

Newspaper format

Spring 2002, 90.9 Wmpg Fm

WMPG Program Guides

Newspaper format

Efficacy Of Interactive Internet-Based Education In Structural Timber Design, Aaron B. Henson, Kenneth J. Fridley, David Pollock, C Jayne Brahler

Faculty Publications - Biomedical, Mechanical, and Civil Engineering

While traditional teaching methods (e.g., real-time, synchronous lectures) have proven effective for training future engineers, the Internet provides an avenue to reinforce the material and augment student learning, comprehension, and retention of material. This paper presents the integration and assessment of a library of interactive instructional modules specifically for a senior-level undergraduate elective course in civil engineering. An ongoing, comprehensive assessment process was implemented in the fall 1999 semester. The results of this quantitative assessment indicate that the use of well designed and pedagogically sound Internet-based supplemental modules provide students with a better understanding of course material. However, when Internet-based …

Santa Clara Magazine, Volume 44 Number 3, Winter 2002, Santa Clara University

Santa Clara Magazine

10 - GLOBALIZATION EMPOWERS GOOD AND EVIL By Rob Elder. Thomas Friedman, Pulitzer Prizewinning author and international affairs columnist for The New York Times, discusses this complex issue during a visit to campus.

14 - ON THE COLLISION OF WORLDS By Fred White. Corny science fiction movies inspire an SCU English professor to ponder deeply cosmic questions.

18 - THE CAMPAIGN FOR SANTA CLARA By Elizabeth Kelley Gillogly '93. SCU launches the largest campaign in its history, with plans for endowed scholarships, a new library, a new building for the Leavey School of Business, and much more.

Use Of Pyrolysis Gc/Ms For Predicting Emission Byproducts From The Incineration Of Double-Base Propellant, Donald Cropek, Patricia Kemme, Jean Day, Jane Cochran

United States Army: Publications

Gas chromatography/mass spectrometry was used to analyze the pyrolytic byproducts from an Army-unique propellant compound (AA2) that is composed of predominantly nitrocellulose and nitroglycerin. Compounds produced by AA2 pyrolysis were compared to compounds detected in the gaseous effluent from AA2 incineration. The light permanent gases and most of the higher molecular weight byproducts produced by AA2 incineration are replicated by laboratory pyrolysis on AA2. The reverse case also holds whereby 18 out of 24 high molecular weight AA2 pyrolytic byproducts are found in the incinerator emissions. Poor matching, however, was obtained between the two processes for the volatile, water-soluble species. …

Enabling Dynamic Market-Managed Qos Interconnection In The Next Generation Internet By A Modified Bgp Mechanism, Junseok Hwang, Jorn Altmann, Huw Oliver, Alfonso Suarez

School of Information Studies - Faculty Scholarship

We propose a market-managed QoS (Quality of Service) interconnection model for heterogeneous networking environments. The deployment of this model will help autonomous systems to reduce the cost of their network services as well as increase social welfare. We describe a technical solution for a next generation Internet, where networks are managed based on either technology requirements (QoS networks) or market principles (market-managed networks). Our solution requires two technologies: BMP (Bandwidth Management Point) and a modified version of BGP (Border Gateway Protocol). The modified version of BGP, as proposed in this paper, provides additional routing exchange information such as price and …

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 18, Number 4, January 2002, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

An eight page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.

Test 1798: John Deere 8320 Diesel 16-Speed, Nebraska Tractor Test Lab

Nebraska Tractor Tests

ABOUT THE TEST REPORT AND USE OF THE DATA

The test data contained in this report are a tabulation of the results of a series of tests. Due to the restricted format of these pages, only a limited amount of data and not all of the tractor specifications are included. The full OECD report contains usually about 30 pages of data and specifications. The test data were obtained for each tractor under similar conditions and therefore, provide a means of comparison of performance based on a limited set of reported data.

EXPLANATION OF THE TEST PROCEDURES

Purpose

The purpose of …

Specification For The Design, Testing, And Utilization Of Industrial Steel Storage Racks, Rack Manufacturers Institute

Rack Manufacturers Institute (RMI) Specifications and Manuals (1984 - 2012)

No abstract provided.

Translation Of 'Balika Badhu: A Selected Anthology Of Bengali Short Stories', Monish Ranjan Chatterjee

Electrical and Computer Engineering Faculty Publications

This project, which began with the desire to render into English a rather long tale by Bimal Kar about five years ago, eventually grew into a considerably more extended compilation of Bengali short stories by 10 of the most well-known practitioners of that art since the heyday of Rabindranath Tagore. The collection is limited in many ways, not the least of which being that no woman writer has been included, and that it contains only a baker's dozen stories (if we count Bonophool's micro-stories collectively as one ) — a number pitifully small considering the vast and prolific field of …

Discontinuities And Continuities: A New Way To Understand Virtual Work, Mary Beth Watson-Manheim, Kevin Crowston, Katherine M. Chudoba

School of Information Studies - Faculty Scholarship

“Virtual” is a potent buzzword, freely applied to many situations, with many meanings. In this exploratory study, we develop a more precise understanding of "virtual" to describe changing work environments. Specifically, we propose a framework to classify work environments based on the type of discontinuities involved. Discontinuities are gaps or a lack of coherence in aspects of work. The framework allows us to compare research across different topics and work settings. We use the framework to classify 75 published articles on virtual work environments or earlier, related research streams. We observed that many studies were simultaneously addressing existing or emerging …

Exploring Strengths And Limits On Open Source Software Engineering Processes: A Research Agenda, Kevin Crowston, Barbara Scozzi

School of Information Studies - Faculty Scholarship

Many researchers have investigated the nature and characteristics of open source software (OSS) projects and their developer communities. In this position paper, after examining some success factors, we discuss potential limits on the replicability and portability of OSS engineering processes. Based on this analysis, we propose a research agenda to better understand the current nature of the processes and thus the strengths and the limitations.