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Articles 26701 - 26730 of 27311
Full-Text Articles in Engineering
University Clean Room Management Program, William P. Acito Jr
University Clean Room Management Program, William P. Acito Jr
Journal of the Microelectronic Engineering Conference
Implementation of a computerized clean room monitoring system at the RIT facility and the benefits of the RIT Management Program are discussed in this paper. Clean room parameters of interest with respect to environment, contamination, and process control were identified and the management of a commercial and university clean room will be contrasted.
Analysis Of Ellipsometer Measurements, Wael A. Bizri
Analysis Of Ellipsometer Measurements, Wael A. Bizri
Journal of the Microelectronic Engineering Conference
A procedure for making A vs v plots to analyze ellipsometer readings was generated. This replaced the look-up tables. The refractive index and thickness were generated using the Mccrackin Ellipsometer program.1 This program was debugged.
Introduction Of Statistical Decision Making And Measurement Control Charts Into Rit Cleanroom Facility, Matthew L. Blair
Introduction Of Statistical Decision Making And Measurement Control Charts Into Rit Cleanroom Facility, Matthew L. Blair
Journal of the Microelectronic Engineering Conference
A computer program was written that would enable the user to generate measurement control charts or make statistical decisions based on the means or variations of two sets of data. Statistical t-test and F-test results were obtained using an experimental example, indicate how this program could be used to aid in engineering decision making. Cleanroom parameters such as temperature, humidity and particle counts were obtained and plotted.
Comparison Of Silicon Dioxide Films, Brian J. Bluff
Comparison Of Silicon Dioxide Films, Brian J. Bluff
Journal of the Microelectronic Engineering Conference
This experiment compared oxides grown at 950 C for 135 minutes and 1100 C for 15 minutes in dry 02. Two different size capacitors were fabricated with gate areas of .OlfOO crrf and ,0225 cm? • The films were compared by capacitance - voltage measurements. It was found that the 1100 C process yielded a flat band voltage shift of l volt less than the 950 C process.
Desgin Of An Ion Implantation Process Monitoring Chip On I.C.E And Provide A Methodology For Evaluation Of Testing Results, Joseph J. Burkis
Desgin Of An Ion Implantation Process Monitoring Chip On I.C.E And Provide A Methodology For Evaluation Of Testing Results, Joseph J. Burkis
Journal of the Microelectronic Engineering Conference
A test chip has been designed for experimental use in determining and maintaing the operation of an ion implanter. The structures on this chip provide information on the implant processing and post implant annealing. Implant does will be monitored using van der PAUW [1] structures, implanted resistors and comparison of threshold adjusted MOSFET with adjacent non adjusted MOSFET. Surface effects and annealing information will be taken from analysis of gated diodes [2].
Post Exposure Silyation Of A Positive Photoresist, Steven D. Carlson
Post Exposure Silyation Of A Positive Photoresist, Steven D. Carlson
Journal of the Microelectronic Engineering Conference
A silylation process employing hexamethyldisilazane (HMDS> as a silylating agent was examined as a ethod of combining the high resolution capabilities of a multilevel resist and the process simplicity of a single layer resist scheme. Atmospheric pressure vapor phase silylation and liquid phase silylation were performed on Kodak 809 Micropositive resist. The vapor phase silylation did not result in significant alteration of the etch characteristics. The liquid phase silylation was performed for several HMDS concentrations in Freon. Liquid phase silylation was shown to provide significant etch selectivity upon exposure to an oxygen plasma.
Ideas To Asics, Kevin Clukey
Ideas To Asics, Kevin Clukey
Journal of the Microelectronic Engineering Conference
The conception/completion/distribution of en Integrated circuit Idea Is the heart of RSIC (application-specific Integrated circuits) technology. Completing the transformation of en Idea to the design before the market window closes Is the designer's greatest concern. The euolution of sophisticated computer-aided design tools hes enabled functional simulation of analog end digital together within hours. R description of the latest software methodologies Is presented through an eHample of e possible RSIC Implementation.
Lateral Transistor Gain Calculations, Thomas A. Estelle
Lateral Transistor Gain Calculations, Thomas A. Estelle
Journal of the Microelectronic Engineering Conference
The gain of lateral transistors is calculated with a program entitled "LATERAL". This program uses a profile generated with SUPREM II, and calculates the depletion region edges and the built in potential for the diffused junctions. The effects included are the base width narrowing due to the applied bias and. recombination in the base. The results are compared with measured gains, and show good agreement. The effects of lifetime in the base are seen to show a large affect on the calculated gain.
Diffusion Staining Techniques, Benjamin G. Eynon Jr
Diffusion Staining Techniques, Benjamin G. Eynon Jr
Journal of the Microelectronic Engineering Conference
Cross-section staining of p-type diffusions was investigated. The method employed a stain formulation of Diffusion depths of 1.9 microns were delineated and photographed using a scanning electron microscope.
Integrated Injection Logic, Mark Grabosky
Integrated Injection Logic, Mark Grabosky
Journal of the Microelectronic Engineering Conference
Since Integrated Injection Logic was developed in 1972, it has found applications in LSI memories, microprocessors, digital wrist watches, AID and DIA converters, and other custom IC's. The characteristics of a typical IIL gate are comparable to those of CMOS devices. Propagation times as low as 63 ns and power consumptions as small as .01 mW per gate have been achieved in well developed IIL processes. The major benefit that IIL has over other logic families is its relative simplicity. A standard IIL process only requires four masks, (base diffusion, emitter diffusion, contact cuts, and metalli2ation>. No isolation is …
Computer Calculation Of Bipolar Transistor Current Gain Using The Transistor Impurity Doping Profile, James Hermanowski
Computer Calculation Of Bipolar Transistor Current Gain Using The Transistor Impurity Doping Profile, James Hermanowski
Journal of the Microelectronic Engineering Conference
A new program, BETA, will calculate a one-dimensional vertical transistor current gain using a modified Gummel approach [1], which incorporates heavy doping effects in the emitter such as band gap narrowing [2]. It is assumed that the base transport factor is equal to one, that the transistor is operating at intermediate current levels, and that the minority carrier lifetime in the emitter is greater than 10 nanoseconds. The gain will be calculated using information from the impurity doping profile generated by SUPREM II. Preliminary results indicate that this approach will give results with less than 25% error.
Design And Modeling Of An Advance Cmos Process, John G. Hock
Design And Modeling Of An Advance Cmos Process, John G. Hock
Journal of the Microelectronic Engineering Conference
An advanced ten level five micron CMOS process was designed. The process was modeled using SUPREM II software to calculate doping profiles, junction depths, and threshold voltages.
Design Of An Advanced Cmos Process Test Chip, William J. Brocklehurst
Design Of An Advanced Cmos Process Test Chip, William J. Brocklehurst
Journal of the Microelectronic Engineering Conference
No abstract provided.
Design And Fabrication Of A Sixteen Bit Pmos Static Ram, Douglas J. Lange
Design And Fabrication Of A Sixteen Bit Pmos Static Ram, Douglas J. Lange
Journal of the Microelectronic Engineering Conference
This project is focused on fabricating a self containing 16 bit PMOS static RAM using 10µm minimum geometries. The basic structure was designed previously but changes had to be made to the CIF files which contained the circuit layout. Diffusion runs were added to allow for connections between inputs /outputs and pads. Alignment marks were also added. MANN files were generated, from which reticles, and finally, the masks were made. The process used to fabricate the SRAM was modelled on SUPREM. SPICE was used to determine the threshol voltage and read/write time. The circuit was then fabricated and tested.
Alternate Optimization Of Process Parameters, Todd J. Layer
Alternate Optimization Of Process Parameters, Todd J. Layer
Journal of the Microelectronic Engineering Conference
Optimization traditionally employs strategies of factorial design that have been shown to be lacking in efficiency. Research into evolutionary operation schemes, a more efficient technique, has been conducted and an alternative strategy for optimization proposed. The procedureis outlined and an application with the computer modeling program SUPREM II is discussed.
Design, Layout And Realization Of An All Nor Enhancement Type Pmos Serial Adder, Steven M. Macaluso
Design, Layout And Realization Of An All Nor Enhancement Type Pmos Serial Adder, Steven M. Macaluso
Journal of the Microelectronic Engineering Conference
A four bit serial adder was designed with PMOS NOR gates from a truth table that models binary serial addition. Three storaqe reqisters were also included in the desiqn, two-four bit shift registers for the incoming digits and one-five bit register for the sum. A simple five gate latch was used for the bits of these registers. The circuit was layed out using ICE , a software program designed to facilitate circuit layout for mask making at R.I.T.
Comparison Of D.I. Water Bacteria Counts By Culture And Fluorescence Microscopy, Paul J. Mager
Comparison Of D.I. Water Bacteria Counts By Culture And Fluorescence Microscopy, Paul J. Mager
Journal of the Microelectronic Engineering Conference
The traditional Culture technique for bacterial enumeration requires prolonged incubation times and only measures viable bacterial densities. In comparison, the technique of Fluorescence Microscopy offers a method for obtaining total bacterfal determinations fn a much shorter time. This paper fs concerned with a preliminary comparison of these two methods.
Mask And Plot Generation On The Calma, Glenn A. Marshall
Mask And Plot Generation On The Calma, Glenn A. Marshall
Journal of the Microelectronic Engineering Conference
The procedures to create hardcopies of designs created on General Electric's CALMA, Computer Aided Design system is discussed. Also addressed is the interfacing of the CALMA to a Mann 3000 Pattern Generator.
Multilayer Resist Imaging Methods, James C. Mckay
Multilayer Resist Imaging Methods, James C. Mckay
Journal of the Microelectronic Engineering Conference
A trilayer imaging system, using DuPont Pyralin polyimide as a planarizing layer, an Allied Chemical Accuglass Spin On Glass barrier layer, and an imaging layer of Kodak 820 positive photoresist, has been previously investigated at RIT. This system failed to perform as expected when the polyimide coating lifted off the metal layer it was designed to mask. This project investigates the process previously used and makes an attempt to qualify it. Along with this, a process is proposed which uses the polyirnide as a lift-off material in a reversal process using the same materials and equipment.
Design Of Experiments And Diffusion Characterization, James M. Mortellaro
Design Of Experiments And Diffusion Characterization, James M. Mortellaro
Journal of the Microelectronic Engineering Conference
An ANOVA and factorial designs for optimization were were compared using a hypothetical LPCVD process situation. The three factorial proved superior Boron diffusion was optimized using the three factorial design.
Contrast Enhancement Material Evaluation For A Micralign Projection System, Karen L. Muniak
Contrast Enhancement Material Evaluation For A Micralign Projection System, Karen L. Muniak
Journal of the Microelectronic Engineering Conference
Contrast Enhancement Material CCEM-388) was to be evaluated for a Perkin Elmer Micralign Projection System by comparing the contrasts for Kodak 820 positive photoresist with and without the use of the CEM. The contrast curve was determined from thickness versus log exposure graphs for various development times. A correlation between exposure dose and carriage speed of the Micralign System was investigated.
A Low Frequency C-V Measurement Technique And Analysis For Surface State Density Determination, Gregg R. Myers
A Low Frequency C-V Measurement Technique And Analysis For Surface State Density Determination, Gregg R. Myers
Journal of the Microelectronic Engineering Conference
A flexible low frequency measurement system was set up for providing high quality low frequency C-V curves suitable for analysis and a method is described to analyze the low frequency C-V response for surface state density calculations. This method was used to calculate surface densities over a large portion of the band gap for several MOS capacitors.
Process Development For A Multi-Level Metal Process, Robert M. Newcomb
Process Development For A Multi-Level Metal Process, Robert M. Newcomb
Journal of the Microelectronic Engineering Conference
Preliminary work on multi-level metal processes using photosensitive polyimide, Kodak 820 resist. Shipley 1400-27 resist, Pyralin polyimide, spin-on glass and evaporated silicon monoxide was reviewed. The results of this analysis yielded some problem areas which were the foundation for this work. Results from an aluminum/spin-on glass/aluminum process show that spin-on glass is a viable dielectric material and that some work is needed to optimize the process.
The Pmos Reference Library For The Rit Calma Cad System, Sassan Nour
The Pmos Reference Library For The Rit Calma Cad System, Sassan Nour
Journal of the Microelectronic Engineering Conference
A reference library of PMOS structures was created on the Calma CAD system. The Library contains NAND, NOR, Inverter, alignment marks, and contact pads. The reference library may be accessed by the users of the system to assist them with their design projects. The cells have been previously studied and fabricated at R!T's department of microelectronic engineering [1].
Growth Of Anodic Al2O3 Films, Bruce Parmelee
Growth Of Anodic Al2O3 Films, Bruce Parmelee
Journal of the Microelectronic Engineering Conference
The anodic oxidation of Aluminum (Al), which is a low temperature process, was used to form an aluminum oxide (Al2O3) film for use as an insulating layer. The anodization was done in a diluted, approximately 10% by volume, sulferic acid solution (H2SO4). Constant anodization voltages of 10, 15, and 20 volts, were maintained to obtain layers of Al2O3 ranging in thickness and refractive index from 3375-4077A and 1.46-1.95 receptively.
Image Reversal With Az5214e Photoresist For Etch And Liftoff, Michael A. Ryan
Image Reversal With Az5214e Photoresist For Etch And Liftoff, Michael A. Ryan
Journal of the Microelectronic Engineering Conference
Aluminum pattern definition was evaluated using AZ5214E photoresfst 1n conventional posfttve and image reversal modes. Wet etch and liftoff strategies were examined for each photolithographic process. Defect density as a function of feature size is given for each process. and yield versus area 1s projected. It was determined that image reversal processing yielded a lower defect density than conventional resist processing for both etch and liftoff processes.
A Five Micron, Self Aligned, Polysilicon Gate Cmos Process Design, John P. Scoopo
A Five Micron, Self Aligned, Polysilicon Gate Cmos Process Design, John P. Scoopo
Journal of the Microelectronic Engineering Conference
The design of a five micron, polysilicon gate, CMOS process is discussed. A p-well approach was used with aoriented n-type substrate as the starting material. Calculations of the threshold adjustment dose and desired doping level of the p-well were based on a desired threshold voltage of -0.8 volts for the p-channel transistor and 0.8 volts for the n-channel device. The desired doping levels of the sources and drains were based on minimizing the parasitic resistances and capacitances associated with a MOS transistor. SUPREM II was used to determine the implant/drive cycles necessary to obtain the required doping profiles and to …
Characterization Of Solid Source Phosphorus Doping Diffusion, Charles G. Smith
Characterization Of Solid Source Phosphorus Doping Diffusion, Charles G. Smith
Journal of the Microelectronic Engineering Conference
Phosphorus solid sources for doping of silicon wafers were characterized by keeping the temperature constant and varying the diffusion time. Sheet resistances and junction depths were measured using a four-point station and the groove and stain method, respectively. The results were contrasted with the SUPREM II predictions.